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ADC122S101CIMM bảng dữ liệu(PDF) 2 Page - Texas Instruments |
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2 / 27 page IN1 IN2 MUX T/H SCLK VA GND CS DIN DOUT CONTROL LOGIC 12-BIT SUCCESSIVE APPROXIMATION ADC GND ADC122S101 SNAS286D – MARCH 2005 – REVISED MARCH 2013 www.ti.com Block Diagram Figure 2. PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS Pin No. Symbol Description ANALOG I/O 5 ,4 IN1 and IN2 Analog inputs. These signals can range from 0V to VA. DIGITAL I/O 8 SCLK Digital clock input. This clock directly controls the conversion and readout processes. Digital data output. The output samples are clocked out of this pin on falling edges of the 7 DOUT SCLK pin. Digital data input. The ADC122S101's Control Register is loaded through this pin on rising 6 DIN edges of the SCLK pin. Chip select. On the falling edge of CS, a conversion process begins. Conversions continue 1 CS as long as CS is held low. POWER SUPPLY Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and 2 VA bypassed to GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located within 1 cm of the power pin. 3 GND The ground return for the die. 2 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: ADC122S101 |
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