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STW5093CYLT bảng dữ liệu(PDF) 10 Page - STMicroelectronics |
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10 / 34 page STw5093 10/34 Table 2. Control Register CR0 Functions *: state at power on initialization (1): significant in companded mode only Table 3. Control Register CR1 Functions *: state at power on initialization (1): significant in companded mode only X: reserved: write 0 76 543 21 0 Function F1 F0 CM MA IA FF B7 DL 0 0 1 1 0 1 0 1 MCLK or AUXCLK = 512 kHz MCLK or AUXCLK = 1.536 MHz MCLK or AUXCLK = 2.048 MHz MCLK or AUXCLK = 2.560 MHz * 0 1 Linear code * Companded code Linear Code Companed Code 0 0 1 1 0 1 0 1 2-complement * sign and magnitude 2-complement 1-complement MU-law: CCITT D3-D4 * MU-law: Bare Coding A-law including even bit inversion A-law: Bare Coding 0 1 B1 and B2 consecutive * (1) B1 and B2 separated (1) 0 1 8 bits time-slot * (1) 7 bits time-slot (1) 0 1 Normal operation * Digital Loop-back * 76 54 32 10 Function DM1 DM0 DO MR MX EN TS SLC 0 1 1 X 0 1 delayed data timing * non-delayed normal data timing non-delayed reverse data timing 0 1 L0 latch set to 1 * L0 latch set to 0 0 1 DR connected to rec. path * CR2 connected to rec. path (1) 0 1 Trans path connected to DX * CR3 connected to DX (1) 0 1 voice data transfer disable * voice data transfer enable 0 1 B1 channel selected * B2 channel selected (1) 0 1 MCLK Master Clock and FS Frame Sync inputs are selected * AUXCLK Auxiliary Clock input is selected |
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