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ADP3335ARMZ-3.3RL7 bảng dữ liệu(PDF) 11 Page - Analog Devices |
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ADP3335ARMZ-3.3RL7 bảng dữ liệu(HTML) 11 Page - Analog Devices |
11 / 16 page Data Sheet ADP3335 Rev. C | Page 11 of 16 PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS All surface-mount packages rely on the traces of the PC board to conduct heat away from the package. Use the following general guidelines when designing printed circuit boards to improve both electrical and thermal performance. 1. Keep the output capacitor as close as possible to the output and ground pins. 2. Keep the input capacitor as close as possible to the input and ground pins. 3. PC board traces with larger cross sectional areas will remove more heat from the ADP3335. For optimum heat transfer, specify thick copper and use wide traces. 4. It is not recommended to use solder mask or silkscreen on the PCB traces adjacent to the ADP3335’s pins, since doing so will increase the junction-to-ambient thermal resistance of the package. 5. Use additional copper layers or planes to reduce the thermal resistance. When connecting to other layers, use multiple vias, if possible. LFCSP LAYOUT CONSIDERATIONS The LFCSP package has an exposed die paddle on the bottom, which efficiently conducts heat to the PCB. In order to achieve the optimum performance from the LFCSP package, special consideration must be given to the layout of the PCB. Use the following layout guidelines for the LFCSP package. 0.50 2 × VIAS, 0.250∅ 35 µm PLATING 3.36 0.90 1.80 2.36 1.90 1.40 0.30 0.73 Figure 25. 3 mm × 3 mm LFCSP Pad Pattern (Dimensions shown in millimeters) 1. The pad pattern is given in Figure 25. The pad dimension should be followed closely for reliable solder joints, while maintaining reasonable clearances to prevent solder bridging. 2. The thermal pad of the LFCSP package provides a low thermal impedance path (approximately 20°C/W) to the PCB. Therefore, the PCB must be properly designed to effectively conduct heat away from the package. This is achieved by adding thermal vias to the PCB, which provide a thermal path to the inner or bottom layers. See Figure 25 for the recommended via pattern. Note that the via diameter is small to prevent the solder from flowing through the via and leaving voids in the thermal pad solder joint. Also, note that the thermal pad is attached to the die substrate, so the thermal planes to which the thermal vias connect must be electrically isolated or tied to VIN. Do NOT connect the thermal pad to ground. 3. The solder mask opening should be about 120 µ (4.7 mils) larger than the pad size, resulting in a minimum 60 µm (2.4 mils) clearance between the pad and the solder mask. 4. The paste mask opening is typically designed to match the pad size used on the peripheral pads of the LFCSP package. This should provide a reliable solder joint as long as the stencil thickness is about 0.125 mm. The paste mask for the thermal pad needs to be designed for the maximum coverage to effectively remove the heat from the package. However, due to the presence of thermal vias and the size of the thermal pad, eliminating voids may not be possible. 5. The recommended paste mask stencil thickness is 0.125 mm. A laser cut stainless steel stencil with trapezoidal walls should be used. A “No Clean” Type 3 solder paste should be used for mounting the LFCSP package. Also, a nitrogen purge during the reflow process is recommended. 6. The package manufacturer recommends that the reflow temperature should not exceed 220°C and the time above liquidus is less than 75 seconds. The preheat ramp should be 3°C/second or lower. The actual temperature profile depends on the board density and must be determined by the assembly house as to what works best. SHUTDOWN MODE Applying a TTL high signal to the shutdown (SD) pin or tying it to the input pin, turns the output ON. Pulling SD down to 0.4 V or below, or tying it to ground, turns the output OFF. In shutdown mode, quiescent current is reduced to a typical value of 10 nA. |
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