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ADG715BRU-REEL bảng dữ liệu(PDF) 6 Page - Analog Devices |
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ADG715BRU-REEL bảng dữ liệu(HTML) 6 Page - Analog Devices |
6 / 16 page ADG714/ADG715 –6– REV. ADG715 TIMING CHARACTERISTICS1 Parameter Limit at TMIN, TMAX Unit Conditions/Comments fSCL 400 kHz max SCL Clock Frequency t1 2.5 μs min SCL Cycle Time t2 0.6 μs min tHIGH, SCL High Time t3 1.3 μs min tLOW, SCL Low Time t4 0.6 μs min tHD, STA, Start/Repeated Start Condition Hold Time t5 100 ns min tSU, DAT, Data Setup Time t6 2 0.9 μs max tHD, DAT, Data Hold Time 0 μs min t7 0.6 μs min tSU, STA, Setup Time for Repeated Start t8 0.6 μs min tSU, STO, Stop Condition Setup Time t9 1.3 μs min tBUF, Bus Free Time Between a STOP Condition and a Start Condition t10 300 ns max tR, Rise Time of Both SCL and SDA When Receiving 20 + 0.1Cb 3 ns min t11 250 ns max tF, Fall Time of SDA When Receiving t11 300 ns max tF, Fall Time of SDA When Transmitting 0.1Cb 3 ns min Cb 400 pF max Capacitive Load for Each Bus Line tSP 4 50 ns max Pulsewidth of Spike Suppressed NOTES 1See Figure 2. 2A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V IH min of the SCL signal) in order to bridge the undefined region of SCL’s falling edge. 3C b is the total capacitance of one bus line in pF. t R and tF measured between 0.3 VDD and 0.7 VDD. 4Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns. Specifications subject to change without notice. SDA SCL START CONDITION REPEATED START CONDITION STOP CONDITION t8 t1 t7 t4 t5 t11 t2 t6 t10 t3 t4 t9 Figure 2. 2-Wire Serial Interface Timing Diagram (VDD = 2.7 V to 5.5 V. All specifications –40 C to +85 C unless otherwise noted.) C |
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