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AD5439YRU-REEL7 bảng dữ liệu(PDF) 5 Page - Analog Devices |
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AD5439YRU-REEL7 bảng dữ liệu(HTML) 5 Page - Analog Devices |
5 / 28 page Data Sheet AD5429/AD5439/AD5449 Rev. E | Page 5 of 28 TIMING CHARACTERISTICS All input signals are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V, temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter1 Limit at TMIN, TMAX Unit Conditions/Comments2 fSCLK 50 MHz max Maximum clock frequency t1 20 ns min SCLK cycle time t2 8 ns min SCLK high time t3 8 ns min SCLK low time t4 13 ns min SYNC falling edge to SCLK falling edge setup time t5 5 ns min Data setup time t6 4 ns min Data hold time t7 5 ns min SYNC rising edge to SCLK falling edge t8 30 ns min Minimum SYNC high time t9 0 ns min SCLK falling edge to LDAC falling edge t10 12 ns min LDAC pulse width t11 10 ns min SCLK falling edge to LDAC rising edge t123 25 ns min SCLK active edge to SDO valid, strong SDO driver 60 ns min SCLK active edge to SDO valid, weak SDO driver t13 12 ns min CLR pulse width t14 4.5 ns min SYNC rising edge to LDAC falling edge Update Rate 2.47 MSPS Consists of cycle time, SYNC high time, data setup, and output voltage settling time 1 Guaranteed by design and characterization, not subject to production test. 2 Falling or rising edge as determined by the control bits of the serial word. Strong or weak SDO driver selected via the control register. 3 Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications are measured with a load circuit, as shown in Figure 5. TIMING DIAGRAMS t1 t2 t3 t7 t8 t4 t5 t6 t9 t10 t11 DB15 DB0 SCLK SDIN LDAC1 LDAC2 SYNC 1ASYNCHRONOUS LDAC UPDATE MODE. 2SYNCHRONOUS LDAC UPDATE MODE. NOTES 1. ALTERNATIVELY, DATA CAN BE CLOCKED INTO THE INPUT SHIFT REGISTER ON THE RISING EDGE OF SCLK AS DETERMINED BY THE CONTROL BITS. TIMING IS AS ABOVE, WITH SCLK INVERTED. Figure 2. Standalone Mode Timing Diagram |
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