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AD5392BCPZ-3 bảng dữ liệu(PDF) 11 Page - Analog Devices

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Giải thích chi tiết về linh kiện  8-/16-Channel, 3 V/5 V, Serial Input, Single-Supply, 12-/14-Bit Voltage Output
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AD5392BCPZ-3 bảng dữ liệu(HTML) 11 Page - Analog Devices

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Data Sheet
AD5390/AD5391/AD5392
Rev. E | Page 11 of 44
TIMING CHARACTERISTICS
SERIAL SPI-, QSPI-, MICROWIRE-, AND DSP-COMPATIBLE INTERFACE
DVDD = 2 V to 5.5 V; AVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 6. 3-Wire Serial Interface1
Parameter2, 3
Limit at TMIN, TMAX
Unit
Description
t1
33
ns min
SCLK cycle time
t2
13
ns min
SCLK high time
t3
13
ns min
SCLK low time
t4
13
ns min
SYNC falling edge to SCLK falling edge setup time
t54
13
ns min
24th SCLK falling edge to SYNC falling edge
t64
33
ns min
Minimum SYNC low time
t7
10
ns min
Minimum SYNC high time
t7
50
ns min
Minimum SYNC high time in readback mode
t8
5
ns min
Data setup time
t9
4.5
ns min
Data hold time
t104
30
ns max
24th SCLK falling edge to BUSY falling edge
t11
670
ns max
BUSY pulse width low (single channel update)
t124
20
ns min
24th SCLK falling edge to LDAC falling edge
t13
20
ns min
LDAC pulse width low
t14
2
μs max
BUSY rising edge to DAC output response time
t15
0
ns min
BUSY rising edge to LDAC falling edge
t16
100
ns min
LDAC falling edge to DAC output response time
t17
8
µs typ
DAC output settling time, AD5390/AD5392
t17
6
µs typ
DAC output settling time, AD5391
t18
20
ns min
CLR pulse width low
t19
40
µs max
CLR pulse activation time
t205
20
ns max
SCLK rising edge to SDO valid
t214
5
ns min
SCLK falling edge to SYNC rising edge
t224
8
ns min
SYNC rising edge to SCLK rising edge
t234
20
ns min
SYNC rising edge to LDAC falling edge
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.2 V.
3
See Figure 2, Figure 3, Figure 4, and Figure 5.
4
Standalone mode only.
5
Daisy-chain mode only.
SDO
SCLK
SYNC
DIN
LDAC
t1
24
48
t3
t2
t21
t22
t7
t4
t8
t9
DB23
DB0
DB23
DB0
DB0
INPUT WORD FOR DAC N
INPUT WORD FOR DAC N+1
UNDEFINED
INPUT WORD FOR DAC N
t20
t23
t13
DB23
Figure 2. Serial Interface Timing Diagram (Daisy-Chain Mode)


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