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FM22LD16-55-BG bảng dữ liệu(PDF) 7 Page - Cypress Semiconductor |
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FM22LD16-55-BG bảng dữ liệu(HTML) 7 Page - Cypress Semiconductor |
7 / 15 page FM22LD16 - 256Kx16 FRAM Document Number: 001-86190 Rev. ** Page 7 of 15 Software Write Protect Timing CE A(17:0) WE DQ(15:0) 24555 Data Data OE 02333 1CCCC 000FF 3EF00 3AAAA 1CCCC 0FF00 00000 3AAAA SRAM Drop-In Replacement The FM22LD16 has been designed to be a drop-in replacement for standard asynchronous SRAMs. The device does not require /CE to toggle for each new address. /CE may remain low indefinitely. While /CE is low, the device automatically detects address changes and a new access is begun. This functionality allows /CE to be grounded as you might with an SRAM. It also allows page mode operation at speeds up to 40MHz. Note that if /CE is tied to ground, the user must be sure /WE is not low at powerup or powerdown events. If /CE and /WE are both low during power cycles, data corruption will occur. Figure 3 shows a pullup resistor on /WE which will keep the pin high during power cycles assuming the MCU/MPU pin tri-states during the reset condition. The pullup resistor value should be chosen to ensure the /WE pin tracks VDD yet a high enough value that the current drawn when /WE is low is not an issue. A 10Kohm resistor draws 330uA when /WE is low and VDD=3.3V. Figure 3. Use of Pullup Resistor on /WE NOTE: If /CE is tied to ground, the user gives up the ability to perform the software write-protect sequence. For applications that require the lowest power consumption, the /CE signal should be active only during memory accesses. The FM22LD16 draws supply current while /CE is low, even if addresses and control signals are static. While /CE is high, the device draws no more than the maximum standby current ISB. The FM22LD16 is backward compatible with the 1Mbit FM20L08 and 256Kbit FM18L08 devices. That is, operating the FM22LD16 with /CE toggling low on every address is perfectly acceptable. The /UB and /LB byte select pins are active for both read and write cycles. They may be used to allow the device to be wired as a 512Kx8 memory. The upper and lower data bytes can be tied together and controlled with the byte selects. Individual byte enables or the next higher address line A(18) may be available from the system processor. DQ(15:8) DQ(7:0) D(7:0) A(17:0) /CE /UB /LB /WE /OE 4Mbit F-RAM FM22LD16 A(18) A(17:0) Figure 4. FM22LD16 Wired as 512Kx8 CE WE OE A(17:0) DQ FM22LD16 VDD MCU/ MPU R |
Số phần tương tự - FM22LD16-55-BG |
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Mô tả tương tự - FM22LD16-55-BG |
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