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TMP175AIDGKR bảng dữ liệu(PDF) 10 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  Digital Temperature Sensor with Two-Wire Interface
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TMP175
TMP75
SBOS288J − JANUARY 2004 − REVISED DECEMBER 2007
www.ti.com
10
TIMING DIAGRAMS
The TMP175 and TMP75 are Two-Wire and SMBus
compatible. Figure 4 to Figure 8 describe the various
operations on the TMP175 and TMP75. Bus definitions are
given below. Parameters for Figure 4 are defined in
Table 13.
Bus Idle: Both SDA and SCL lines remain HIGH.
Start Data Transfer: A change in the state of the SDA line,
from HIGH to LOW, while the SCL line is HIGH, defines a
START condition. Each data transfer is initiated with a
START condition.
Stop Data Transfer: A change in the state of the SDA line
from LOW to HIGH while the SCL line is HIGH defines a
STOP condition. Each data transfer is terminated with a
repeated START or STOP condition.
Data Transfer: The number of data bytes transferred
between a START and a STOP condition is not limited and
is determined by the master device. The receiver
acknowledges the transfer of data.
Acknowledge: Each receiving device, when addressed,
is obliged to generate an Acknowledge bit. A device that
acknowledges must pull down the SDA line during the
Acknowledge clock pulse in such a way that the SDA line
is stable LOW during the HIGH period of the Acknowledge
clock pulse. Setup and hold times must be taken into
account. On a master receive, the termination of the data
transfer can be signaled by the master generating a
Not-Acknowledge on the last byte that has been
transmitted by the slave.
PARAMETER
FAST MODE
HIGH-SPEED MODE
UNITS
PARAMETER
MIN
MAX
MIN
MAX
UNITS
SCL Operating Frequency
f(SCL)
0.001
0.4
0.001
3.4
MHz
Bus Free Time Between STOP and START Condition
t(BUF)
600
160
ns
Hold time after repeated START condition.
After this period, the first clock is generated.
t(HDSTA)
100
100
ns
Repeated START Condition Setup Time
t(SUSTA)
100
100
ns
STOP Condition Setup Time
t(SUSTO)
100
100
ns
Data Hold Time
t(HDDAT)
0
0
ns
Data Setup Time
t(SUDAT)
100
10
ns
SCL Clock LOW Period
t(LOW)
1300
160
ns
SCL Clock HIGH Period
t(HIGH)
600
60
ns
Clock/Data Fall Time
tF
300
160
ns
Clock/Data Rise Time
tR
300
160
ns
for SCLK
≤ 100kHz
tR
1000
ns
Table 13. Timing Diagram Definitions for the TMP175 and TMP75
TWO-WIRE TIMING DIAGRAMS
SCL
SDA
t
(LOW)
t
R
t
F
t
(HDSTA)
t
(HDSTA)
t
(HDDAT)
t
(BU F )
t
(SUDAT)
t
(HIGH)
t
(SUSTA)
t
(SUSTO)
PS
SP
Figure 4. Two-Wire Timing Diagram


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