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LMX2306 bảng dữ liệu(PDF) 2 Page - Texas Instruments |
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LMX2306 bảng dữ liệu(HTML) 2 Page - Texas Instruments |
2 / 19 page OBSOLETE LMX2306, LMX2316, LMX2326 SNAS016G – MAY 2000 – REVISED APRIL 2013 www.ti.com Connection Diagrams LMX2306/16/26 LMX2306/16/26 Figure 1. 16-Lead (0.173” Wide) Thin Shrink Small Figure 2. 16-pin Chip Scale Package Outline Pkg - TSSOP PLGA See Package Number PW See Package Number NPG Pin Descriptions 16-Pin 16-Pin Pin I/ Description TSSOP PLGA Name O 1 15 FLo O FastLock Output. For connection of parallel resistor to the loop filter. (See FastLock Modes description.) 2 16 CPo O Charge Pump Output. For connection to a loop filter for driving the input of an external VCO. 3 1 GND Charge Pump Ground. 4 2 GND Analog Ground. 5 3 fIN I RF Prescaler Complementary Input. A bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. The complementary input can be left unbypassed, with some degradation in RF sensitivity. 6 4 fIN I RF Prescaler Input. Small signal input from the VCO. 7 5 VCC1 Analog Power Supply Voltage Input. Input may range from 2.3V to 5.5V. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. VCC1 must equal VCC2. 8 6 OSCIN I Oscillator Input. This input is a CMOS input with a threshold of approximately VCC/2 and an equivalent 100k input resistance. The oscillator input is driven from a reference oscillator. 9 7 GND Digital Ground. 10 8 CE I Chip Enable. A LOW on CE powers down the device and will tri-state the charge pump output. Taking CE HIGH will power up the device depending on the status of the power down bit F2. (See Powerdown Operation and DEVICE PROGRAMMING AFTER FIRST APPLYING Vcc.) 11 9 Clock I High Impedance CMOS Clock Input. Data for the various counters is clocked in on the rising edge into the 21-bit shift register. 12 10 Data I Binary Serial Data Input. Data entered MSB first. The last two bits are the control bits. High impedance CMOS input. 13 11 LE I Load Enable CMOS Input. When LE goes HIGH, data stored in the shift registers is loaded into one of the 3 appropriate latches (control bit dependent). 14 12 Fo/LD O Multiplexed Output of the RF Programmable or Reference Dividers and Lock Detect. CMOS output. (See Table 4.) 15 13 VCC2 Digital Power Supply Voltage Input. Input may range from 2.3V to 5.5V. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. VCC1 must equal VCC2. 16 14 VP Power Supply for Charge Pump. Must be ≥ VCC. 2 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LMX2306 LMX2316 LMX2326 |
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