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ADS41B29
ADS41B49
www.ti.com
SBAS486E – NOVEMBER 2009 – REVISED JULY 2012
14-/12-Bit, 250MSPS, Ultralow-Power ADC
with Analog Buffers
Check for Samples: ADS41B29, ADS41B49
1
FEATURES
DESCRIPTION
The ADS41B29/B49 are members of the ultralow-
23
ADS41B49: 14-Bit, 250MSPS
power ADS4xxx analog-to-digital converter (ADC)
ADS41B29: 12-Bit, 250MSPS
family, featuring integrated analog input buffers.
Integrated High-Impedance
These devices use innovative design techniques to
Analog Input Buffer:
achieve high dynamic performance, while consuming
extremely low power. The analog input pins have
Input Capacitance: 2pF
buffers, with benefits of constant performance and
200MHz Input Resistance: 3k
Ω
input impedance across a wide frequency range. The
Maximum Sample Rate: 250MSPS
devices
are
well-suited
for
multi-carrier,
wide
Ultralow Power:
bandwidth communications applications such as PA
linearization.
1.8V Analog Power: 180mW
The ADS41B49/29 have features such as digital gain
3.3V Buffer Power: 96mW
and offset correction. The gain option can be used to
I/O Power: 135mW (DDR LVDS)
improve SFDR performance at lower full-scale input
High Dynamic Performance:
ranges, especially at high input frequencies. The
SNR: 69dBFS at 170MHz
integrated dc offset correction loop can be used to
estimate and cancel the ADC offset. At lower
SFDR: 82.5dBc at 170MHz
sampling rates, the ADC automatically operates at
Output Interface:
scaled-down power with no loss in performance.
Double Data Rate (DDR) LVDS with
The devices support both double data rate (DDR)
Programmable Swing and Strength:
low-voltage differential signaling (LVDS) and parallel
Standard Swing: 350mV
CMOS digital output interfaces. The low data rate of
the DDR LVDS interface (maximum 500MBPS)
Low Swing: 200mV
makes it possible to use low-cost field-programmable
Default Strength: 100
Ω Termination
gate array (FPGA)-based receivers. The devices
2x Strength: 50
Ω Termination
have a low-swing LVDS mode that can be used to
1.8V Parallel CMOS Interface Also
further reduce the power consumption. The strength
of the LVDS output buffers can also be increased to
Supported
support 50
Ω differential termination.
Programmable Gain for SNR/SFDR Trade-Off
The devices are available in a compact QFN-48
DC Offset Correction
package
and
are
specified
over
the
industrial
Supports Low Input Clock Amplitude
temperature range (–40°C to +85°C).
Package: QFN-48 (7mm × 7mm)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PowerPAD is a trademark of Texas Instruments, Incorporated.
3
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2009–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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