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ADS41B49 bảng dữ liệu(PDF) 3 Page - Texas Instruments |
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ADS41B49 bảng dữ liệu(HTML) 3 Page - Texas Instruments |
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3 / 65 page  ADS41B29 ADS41B49 www.ti.com SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 RECOMMENDED OPERATING CONDITIONS ADS41B29, ADS41B49 MIN TYP MAX UNIT SUPPLIES AVDD Analog supply voltage 1.7 1.8 1.9 V AVDD_BUF Analog buffer supply voltage 3 3.3 3.6 V DRVDD Digital supply voltage 1.7 1.8 1.9 V ANALOG INPUTS Differential input voltage range(1) 1.5 VPP Input common-mode voltage 1.7 ± 0.05 V Maximum analog input frequency with 1.5VPP input amplitude (2) 400 MHz Maximum analog input frequency with 1VPP input amplitude (2) 600 MHz CLOCK INPUT Low-speed mode enabled(3) 20 80 MSPS ADS41B29/ ADS41B49 Low-speed mode disabled(3) > 80 250 MSPS Input clock amplitude differential (VCLKP – VCLKM) Sine wave, ac-coupled 0.2 1.5 VPP LVPECL, ac-coupled 1.6 VPP LVDS, ac-coupled 0.7 VPP LVCMOS, single-ended, ac-coupled 1.8 V Low-speed mode enabled 40 50 60 % Input clock duty cycle Low-speed mode disabled 35 50 65 % DIGITAL OUTPUTS CLOAD Maximum external load capacitance from each output pin to DRGND 5 pF Differential load resistance between the LVDS output pairs RLOAD 100 Ω (LVDS mode) TA Operating free-air temperature –40 +85 °C HIGH-PERFORMANCE MODES(4)(5)(6) Set the MODE 1 register bits to get the best performance across sample MODE 1 clock and input signal frequencies. Register address = 03h, register data = 03h. Set the MODE 2 register bit to get the best performance at high input signal MODE 2 frequencies greater than 230MHz. Register address = 4Ah, register data = 01h. (1) With 0dB gain. See the Gain for SFDR/SNR Trade-Off section in Application Information for the relationship between input voltage range and gain. (2) See the Theory of Operation section in the Application Information. (3) See the Serial Interface section for details on the low-speed mode. (4) It is recommended to use these modes to get best performance. These modes can only be set with the serial interface. (5) See the Serial Interface section for details on register programming. (6) Note that these modes cannot be set when the serial interface is not used (when the RESET pin is tied high); see the Device Configuration section. Copyright © 2009–2012, Texas Instruments Incorporated 3 |
Số phần tương tự - ADS41B49_13 |
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Mô tả tương tự - ADS41B49_13 |
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