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93LC86A bảng dữ liệu(PDF) 11 Page - Microchip Technology |
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93LC86A bảng dữ liệu(HTML) 11 Page - Microchip Technology |
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11 / 38 page  2003-2012 Microchip Technology Inc. DS21797L-page 11 93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C 3.0 PIN DESCRIPTIONS TABLE 3-1: PIN DESCRIPTIONS 3.1 Chip Select (CS) A high level selects the device; a low level deselects the device and forces it into Standby mode. However, a programming cycle which is already in progress will be completed, regardless of the Chip Select (CS) input signal. If CS is brought low during a program cycle, the device will go into Standby mode as soon as the programming cycle is completed. CS must be low for 250 ns minimum (TCSL) between consecutive instructions. If CS is low, the internal control logic is held in a Reset status. 3.2 Serial Clock (CLK) The Serial Clock is used to synchronize the communi- cation between a master device and the 93XX series device. Opcodes, address and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK. CLK can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (TCKH) and clock low time (TCKL). This gives the controlling master freedom in preparing opcode, address and data. CLK is a “don't care” if CS is low (device deselected). If CS is high, but the Start condition has not been detected (DI = 0), any number of clock cycles can be received by the device without changing its status (i.e., waiting for a Start condition). CLK cycles are not required during the self-timed write (i.e., auto erase/write) cycle. After detection of a Start condition the specified number of clock cycles (respectively low-to-high transitions of CLK) must be provided. These clock cycles are required to clock in all required opcode, address and data bits before an instruction is executed. CLK and DI then become “don't care” inputs waiting for a new Start condition to be detected. 3.3 Data In (DI) Data In (DI) is used to clock in a Start bit, opcode, address and data, synchronously with the CLK input. 3.4 Data Out (DO) Data Out (DO) is used in the Read mode to output data synchronously with the CLK input (TPD after the positive edge of CLK). This pin also provides Ready/Busy status information during erase and write cycles. Ready/Busy status information is available on the DO pin if CS is brought high after being low for minimum Chip Select low time (TCSL), and an erase or write operation has been initiated. The Status signal is not available on DO if CS is held low during the entire erase or write cycle. In this case, DO is in the High-Z mode. If status is checked after the erase/write cycle, the data line will be high to indicate the device is ready. 3.5 Organization (ORG) When the ORG pin is connected to VCC or logic high, the (x16) memory organization is selected. When the ORG pin is tied to VSS or logic low, the (x8) memory organization is selected. For proper operation, ORG must be tied to a valid logic level. 93XX86A devices are always (x8) organization and 93XX86B devices are always (x16) organization. Name PDIP SOIC TSSOP MSOP DFN(1) TDFN(1) SOT-23 Function CS 1 1 1 1 1 1 5 Chip Select CLK 2 2 2 2 2 2 4 Serial Clock DI 3 3 3 3 3 3 3 Data In DO 4 4 4 4 4 4 1 Data Out VSS 5 5 5 5 5 5 2 Ground ORG 6 6 6 6 6 6 — Organization/93XX86C only PE 7 7 7 7 7 7 — Program Enable/93XX86C only VCC 8 8 8 8 8 8 6 Power Supply Note 1: The exposed pad on the DFN/TDFN package may be connected to Vss or left floating. Note: After a programming cycle is complete, issuing a Start bit and then taking CS low will clear the Ready/Busy status from DO. |
Số phần tương tự - 93LC86A |
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Mô tả tương tự - 93LC86A |
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