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ADAU1461 bảng dữ liệu(PDF) 9 Page - Analog Devices |
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ADAU1461 bảng dữ liệu(HTML) 9 Page - Analog Devices |
9 / 88 page ADAU1461 Rev. 0 | Page 9 of 88 DIGITAL TIMING SPECIFICATIONS −40°C < TA < +105°C, IOVDD = 3.3 V ± 10%. Table 6. Digital Timing Parameter Limit Unit Description tMIN tMAX MASTER CLOCK tMP 74 488 ns MCLK period, 256 × fS mode. tMP 37 244 ns MCLK period, 512 × fS mode. tMP 24.7 162.7 ns MCLK period, 768 × fS mode. tMP 18.5 122 ns MCLK period, 1024 × fS mode. SERIAL PORT tBIL 5 ns BCLK pulse width low. tBIH 5 ns BCLK pulse width high. tLIS 5 ns LRCLK setup. Time to BCLK rising. tLIH 5 ns LRCLK hold. Time from BCLK rising. tSIS 5 ns DAC_SDATA setup. Time to BCLK rising. tSIH 5 ns DAC_SDATA hold. Time from BCLK rising. tSODM 50 ns ADC_SDATA delay. Time from BCLK falling in master mode. SPI PORT fCCLK 10 MHz CCLK frequency. tCCPL 10 ns CCLK pulse width low. tCCPH 10 ns CCLK pulse width high. tCLS 5 ns CLATCH setup. Time to CCLK rising. tCLH 10 ns CLATCH hold. Time from CCLK rising. tCLPH 10 ns CLATCH pulse width high. tCDS 5 ns CDATA setup. Time to CCLK rising. tCDH 5 ns CDATA hold. Time from CCLK rising. tCOD 50 ns COUT three-stated. Time from CLATCH rising. I2C PORT fSCL 400 kHz SCL frequency. tSCLH 0.6 μs SCL high. tSCLL 1.3 μs SCL low. tSCS 0.6 μs Setup time; relevant for repeated start condition. tSCH 0.6 μs Hold time. After this period, the first clock is generated. tDS 100 ns Data setup time. tSCR 300 ns SCL rise time. tSCF 300 ns SCL fall time. tSDR 300 ns SDA rise time. tSDF 300 ns SDA fall time. tBFT 0.6 μs Bus-free time. Time between stop and start. DIGITAL MICROPHONE RLOAD = 1 MΩ, CLOAD = 14 pF. tDCF 10 ns Digital microphone clock fall time. tDCR 10 ns Digital microphone clock rise time. tDDV 22 30 ns Digital microphone delay time for valid data. tDDH 0 12 ns Digital microphone delay time for data three-stated. |
Số phần tương tự - ADAU1461 |
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Mô tả tương tự - ADAU1461 |
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