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AD9888KSZ-170 bảng dữ liệu(PDF) 5 Page - Analog Devices |
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AD9888KSZ-170 bảng dữ liệu(HTML) 5 Page - Analog Devices |
5 / 36 page Data Sheet AD9888 Rev. C | Page 5 of 36 AD9888KSZ-100/-1401 AD9888KSZ-170 Parameter Temp Test Level Min Typ Max Min Typ Max Unit DIGITAL INPUTS Full Input Voltage, High (VIH) Full VI 2.5 2.5 V Input Voltage, Low (VIL) Full VI 0.8 0.8 V Input Current, High (IIH) Full IV −1.0 −1.0 μA Input Current, Low (IIL) Full IV +1.0 +1.0 μA Input Capacitance 25°C V 3 3 pF DIGITAL OUTPUTS Output Voltage, High (VOH) Full VI VD − 0.1 VD − 0.1 V Output Voltage, Low (VOL) Full VI 0.1 V Duty Cycle Full DATACK, DATACK Full IV 44 49 55 44 49 55 % Output Coding Full IV Binary Binary POWER SUPPLY Analog Power Supply Voltage (VD) Full IV 3.0 3.3 3.6 3.0 3.3 3.6 V Output Power Supply Voltage (VDD) Full IV 2.2 3.3 3.6 2.2 3.3 3.6 V PLL Power Supply Voltage (PVD) Full IV 3.0 3.3 3.6 3.0 3.3 3.6 V Analog Power Supply Current (ID) 25°C 200 215 mA Output Power Supply Current (IDD)4 25°C 50 55 mA PLL Power Supply Current (IPVD) 25°C 8 9 mA Total Power Dissipation Full VI 850 1050 920 1150 mW Power-Down Supply Current Full VI 12 20 12 20 mA Power-Down Dissipation Full VI 40 66 40 66 mW DYNAMIC PERFORMANCE Analog Bandwidth, Full Power5 25°C V 500 500 MHz Transient Response 25°C V 2 2 ns Overvoltage Recovery Time 25°C V 1.5 1.5 ns Signal-to-Noise Ratio (SNR)6 25°C IV 42 45 41 44 dB Without Harmonics, fIN = 40.7 MHz Full V 44 43 dB Crosstalk Full V 50 50 dBc THERMAL CHARACTERISTICS Junction-to-Case Thermal Resistance (θJC) V 8.4 8.4 °C/W Junction-to-Ambient Thermal Resistance (θJA) V 35 35 °C/W 1 AD9888JS-100 specifications are tested at 100 MHz. AD9888KS-140 specifications are tested at 140 MHz. 2 See Figure 2. 3 The maximum specifications for the AD9888KS-100 and AD9888KS-140 were obtained with VCO range = 10, charge pump current = 100, PLL divider = 1693. The maximum specifications for the AD9888KS-170 were obtained with VCO range = 11, charge pump current = 100, PLL divider = 2159. 4 DEMUX = 1, DATACK and DATACK load = 15 pF, data load = 5 pF. 5 Maximum bandwidth setting. Bandwidth can also be programmed to 300 MHz, 150 MHz, or 75 MHz. 6 Using an external pixel clock. tSTAH tDHO tDSU tSTASU tSTOSU SCL SDA tBUFF tDAL tDAH Figure 2. Serial Port Read/Write Timing |
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