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AD5421CREZ bảng dữ liệu(PDF) 6 Page - Analog Devices |
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AD5421CREZ bảng dữ liệu(HTML) 6 Page - Analog Devices |
6 / 36 page AD5421 Data Sheet Rev. F | Page 6 of 36 Parameter1 Min Typ Max Unit Test Conditions/Comments REGOUT OUTPUT Voltage regulator output Output Voltage 1.8 12 V See Table 10 Output Voltage TC3 110 ppm/°C Output Voltage Accuracy −4 ±2 +4 % Externally Available Current3, 6 3.15 mA Assuming 4 mA flowing in the loop and during HART communications Short-Circuit Current 23 mA Line Regulation3 500 μV/V Internal NMOS 10 μV/V External NMOS Load Regulation3 8 mV/mA Inductive Load 50 mH Stable operation Capacitive Load 2 10 µF Recommended operation ADC ACCURACY Die Temperature ±5 °C VLOOP Input ±1 % DVDD OUTPUT Can be overdriven up to 5.5 V Output Voltage 3.17 3.3 3.48 V Externally Available Current3, 6 3.15 mA Assuming 4 mA flowing in the loop and during HART communications Short-Circuit Current 7.7 mA Load Regulation 45 mV/mA Measured at 0 mA and 3 mA loads DIGITAL INPUTS3 SCLK, SYNC, SDIN, LDAC Input High Voltage, VIH 0.7 × IODVDD V Input Low Voltage, VIL 0.25 × IODVDD V Hysteresis 0.21 V IODVDD = 1.8 V 0.63 V IODVDD = 3.3 V 1.46 V IODVDD = 5.5 V Input Current −0.015 +0.015 µA Per pin Pin Capacitance 5 pF Per pin DIGITAL OUTPUTS3 SDO Pin Output Low Voltage, VOL 0.4 V Output High Voltage, VOH IODVDD − 0.5 V High Impedance Leakage Current −0.01 +0.01 µA High Impedance Output Capacitance 5 pF FAULT Pin Output Low Voltage, VOL 0.4 V Output High Voltage, VOH IODVDD − 0.5 V FAULT THRESHOLDS ILOOP Under ILOOP − 0.01% FSR mA ILOOP Over ILOOP + 0.01% FSR mA Temp 140°C 133 °C Fault removed when temperature ≤ 125°C Temp 100°C 90 °C Fault removed when temperature ≤ 85°C VLOOP 6V 0.3 V Fault removed when VLOOP ≥ 0.4 V VLOOP 12V 0.6 V Fault removed when VLOOP ≥ 0.7 V |
Số phần tương tự - AD5421CREZ |
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Mô tả tương tự - AD5421CREZ |
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