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AD5330BRU-REEL7 bảng dữ liệu(PDF) 1 Page - Analog Devices |
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AD5330BRU-REEL7 bảng dữ liệu(HTML) 1 Page - Analog Devices |
1 / 28 page 2.5 V to 5.5 V, 115 μA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs AD5330/AD5331/AD5340/AD5341 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2000–2008 Analog Devices, Inc. All rights reserved. FEATURES AD5330: single 8-bit DAC in 20-lead TSSOP AD5331: single 10-bit DAC in 20-lead TSSOP AD5340: single 12-bit DAC in 24-lead TSSOP AD5341: single 12-bit DAC in 20-lead TSSOP Low power operation: 115 μA @ 3 V, 140 μA @ 5 V Power-down to 80 nA @ 3 V, 200 nA @ 5 V via PD Pin 2.5 V to 5.5 V power supply Double-buffered input logic Guaranteed monotonic by design over all codes Buffered/unbuffered reference input options Output range: 0 V to VREF or 0 V to 2 × VREF Power-on reset to 0 V Simultaneous update of DAC outputs via LDAC pin Asynchronous CLR facility Low power parallel data interface On-chip rail-to-rail output buffer amplifiers Temperature range: −40°C to +105°C APPLICATIONS Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators Industrial process control GENERAL DESCRIPTION The AD5330/AD5331/AD5340/AD53411 are single 8-/10-/12- bit DACs. They operate from a 2.5 V to 5.5 V supply consuming just 115 μA at 3 V and feature a power-down mode that further reduces the current to 80 nA. The devices incorporate an on-chip output buffer that can drive the output to both supply rails, but the AD5330, AD5340, and AD5341 allow a choice of buffered or unbuffered reference input. The AD5330/AD5331/AD5340/AD5341 have a parallel interface. CS selects the device and data is loaded into the input registers on the rising edge of WR. The GAIN pin allows the output range to be set at 0 V to VREF or 0 V to 2 × VREF. Input data to the DACs is double-buffered, allowing simultane- ous update of multiple DACs in a system using the LDAC pin. An asynchronous CLR input is also provided, which resets the contents of the input register and the DAC register to all zeros. These devices also incorporate a power-on reset circuit that ensures that the DAC output powers on to 0 V and remains there until valid data is written to the device. The AD5330/AD5331/AD5340/AD5341 are available in thin shrink small outline packages (TSSOP). 1 Protected by U.S. Patent Number 5,969,657. FUNCTIONAL BLOCK DIAGRAM BUFFER 8-BIT DAC DAC REGISTER INPUT REGISTER POWER-DOWN LOGIC BUF GAIN DB7 DB0 .. CS WR CLR LDAC VREF VDD VOUT PD GND AD5330 POWER-ON RESET RESET 10 9 7 6 13 20 8 1 3 12 4 11 5 Figure 1. AD5330 |
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