công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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FDC6320 bảng dữ liệu(PDF) 3 Page - Fairchild Semiconductor |
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FDC6320 bảng dữ liệu(HTML) 3 Page - Fairchild Semiconductor |
3 / 7 page DMOS Electrical Characteristics (T A = 25 O C unless otherwise noted ) Symbol Parameter Conditions Type Min Typ Max Units SWITCHING CHARACTERISTICS (Note 2) t D(on) Turn - On Delay Time N-Channel N-Ch 5 11 nS V DD = 6 V, ID = 0.5 A, P-Ch 6 12 t r Turn - On Rise Time V GS = 4.5 V, RGEN = 50 Ω N-Ch 4.5 10 nS P-Ch 6 12 t D(off) Turn - Off Delay Time P-Channel N-Ch 4 10 nS V DD = -6 V, ID = -0.5 A, P-Ch 7.4 15 t f Turn - Off Fall Time V GEN= -4.5 V, RGEN = 50 Ω N-Ch 3.2 8 nS P-Ch 4 10 Q g Total Gate Charge N-Channel V DS = 5 V, I D = 0.2 A, VGS = 4.5 V P-Channel V DS = -5 V, I D = -0.2A, VGS = -4.5 V N-Ch 0.29 0.4 nC P-Ch 0.23 0.32 Q gs Gate-Source Charge N-Ch 0.105 nC P-Ch 0.12 Q gd Gate-Drain Charge N-Ch 0.045 nC P-Ch 0.03 DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS I S Maximum Continuous Drain-Source Diode Forward Current N-Ch 0.5 A P-Ch -0.5 V SD Drain-Source Diode Forward Voltage V GS = 0 V, IS = 0.5 A (Note 2) N-Ch 0.97 1.3 V V GS = 0 V, IS = -0.5 A (Note 2) P-Ch -1 -1.3 Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. Typical RθJA using the board layouts shown below on FR-4 PCB in a still air environment: Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. FDC6320C.Rev C b. 180 OC/W on a 0.005 in2 of pad of 2oz copper. a. 140 OC/W on a 0.125 in2 pad of 2oz copper. |
Số phần tương tự - FDC6320 |
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Mô tả tương tự - FDC6320 |
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