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FDC6320C bảng dữ liệu(PDF) 1 Page - Fairchild Semiconductor |
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FDC6320C bảng dữ liệu(HTML) 1 Page - Fairchild Semiconductor |
1 / 7 page October 1997 FDC6320C Dual N & P Channel , Digital FET General Description Features Absolute Maximum Ratings T A = 25 oC unless other wise noted Symbol Parameter N-Channel P-Channel Units V DSS, VCC Drain-Source Voltage, Power Supply Voltage 25 -25 V V GSS, VIN Gate-Source Voltage, 8 -8 V I D, IO Drain/Output Current - Continuous 0.22 -0.12 A - Pulsed 0.5 -0.5 P D Maximum Power Dissipation (Note 1a) 0.9 W (Note 1b) 0.7 T J,TSTG Operating and Storage Tempature Ranger -55 to 150 °C ESD Electrostatic Discharge Rating MIL-STD-883D Human Body Model (100pf / 1500 Ohm) 6 kV THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 140 °C/W RθJC Thermal Resistance, Junction-to-Case (Note 1) 60 °C/W FDC6320C.Rev C N-Ch 25 V, 0.22 A, R DS(ON) = 5 Ω @ VGS= 2.7 V. P-Ch 25 V, -0.12 A, R DS(ON) = 13 Ω @ VGS= -2.7 V. Very low level gate drive requirements allowing direct operation in 3 V circuits. V GS(th) < 1.5 V. Gate-Source Zener for ESD ruggedness. >6kV Human Body Model Replace NPN & PNP digital transistors. These dual N & P Channel logic level enhancement mode field effec transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. The device is an improved design especially for low voltage applications as a replacement for bipolar digital transistors in load switching applications. Since bias resistors are not required, this dual digital FET can replace several digital transistors with difference bias resistors. SOT-23 SuperSOT TM-8 SOIC-16 SO-8 SOT-223 SuperSOT TM-6 1 5 3 2 6 4 © 1997 Fairchild Semiconductor Corporation |
Số phần tương tự - FDC6320C |
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Mô tả tương tự - FDC6320C |
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