A--160

Programmable Controller

CQM1H

J

CPU UNIT SPECIFICATIONS

Characteristics

Item

Specifications

Control method

Stored program method

I/O control method

Cyclic scan and direct output/immediate interrupt processing

Programming language

Ladder-diagram programming

I/O capacity

CQM1H-CPU11/21: 256

CQM1H-CPU51/61: 512

Program capacity

CQM1H-CPU11/21 : 3.2 kwords

CQM1H-CPU51

: 7.2 kwords

CQM1H-CPU61

: 15.2 kwords

User data memory capacity

CQM1H-CPU11/21 : 3 kwords

CQM1H-CPU51

: 6 kwords

CQM1H-CPU61

: 12 kwords (DM: 6 kwords; EM: 6 kwords)

Instruction length

1 step per instruction, 1 to 4 words per instruction

Number of instructions

162 (14 basic, 148 special instructions)

Instruction execution times

Basic instructions:

0.375 to 1.125

µs

Special instructions: 17.7

µs (MOV instruction)

Overseeing time

0.70 ms

Mounting structure

No backplane (Modules are joined horizontally using connectors)

Mounting

DIN Track mounting (screw mounting not possible)

CPU built-in DC input points

16

Maximum number of modules

Maximum of 11 modules total for I/O modules and Dedicated I/O modules

Inner Boards

CQM1H-CPU11/21: None

CQM1H-CPU51/61: 2 Boards

Communications modules

(Controller Link Module)

CQM1H-CPU11/21: None

CQM1H-CPU51/61: 1 module

Types of

interrupts

Input interrupts

(4 inputs max.)

Input Interrupt Mode:

Interrupts are executed in response to inputs from external sources to the CPU’s built-in input

points.

Counter Mode:

Interrupts are executed in response to reception of a set number of pulses (counted down) via the

CPU’s internal built-in input points (4 points).

Interval timer

interrupts

(3 timers max.)

Scheduled Interrupt Mode:

Program is interrupted at regular intervals measured by one of the CPU’s internal timers.

One-shot Interrupt Mode:

An interrupt is executed after a set time, measured by one of the CPU’s internal timers.

High-speed counter

interrupts

Target Value Comparison:

Interrupt is executed when the high-speed counter PV is equal to a specified value.

Range Comparison:

Interrupt is executed when the high-speed counter PV lies within a specified range.

Counting is possible for high-speed counter inputs from the CPU’s internal input points, Pulse I/O

Boards, or Absolute Encoder Interface Boards. (The High-speed Counter Board has no interrupt

function, but can output bit patterns internally and externally.)

I/O allocations

I/O is automatically allocated in order from the Unit nearest to the CPU. (Because there are no I/O

tables, it is not necessary to create I/O tables from a Programming Device.)