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DM74ALS646 bảng dữ liệu(PDF) 1 Page - Fairchild Semiconductor |
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DM74ALS646 bảng dữ liệu(HTML) 1 Page - Fairchild Semiconductor |
1 / 6 page © 2000 Fairchild Semiconductor Corporation DS009172 www.fairchildsemi.com October 1986 Revised February 2000 DM74ALS646 Octal 3-STATE Bus Transceiver and Register General Description This device incorporates an octal bus transceiver and an octal D-type register configured to enable multiplexed transmission of data from bus to bus or internal register to bus. This bus transceiver features totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or rela- tively low-impedance loads. The high-impedance state and increased high-logic level drive provides this device with the capability of being connected directly to and driving the bus lines in a bus-organized system without the need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidi- rectional bus drivers, and working registers. The registers in the DM74ALS646 are edge-triggered D- type flip-flops. On the positive transition of the clock (CAB or CBA), the input bus data is stored into the appropriate register. The CAB input controls the transfer of data into the A register and the CBA input controls the B register. The SAB and SBA control pins are provided to select whether real-time data or stored data is transferred. A LOW input level selects real-time data, and a HIGH level selects stored data. The select controls have a “make before break” configuration to eliminate a glitch which would nor- mally occur in a typical multiplexer during the transition between store and real-time data. The enable G and direction control pins provide four modes of operation: real-time data transfer from bus A to B, real- time data transfer from bus B to A, real-time bus A and/or B data transfer to internal storage, or internally stored data transfer to bus A or B. When the enable G pin is LOW, the direction pin selects which bus receives data. When the enable G pin is HIGH, both buses become disabled yet their input function is still enabled. Features s Switching specifications at 50 pF s Switching specifications guaranteed over full tempera- ture and VCC range s Advanced oxide-isolated, ion-implanted Schottky TTL process s 3-STATE buffer outputs drive bus lines directly s Multiplexed real-time and stored data s Independent registers for A and B buses Ordering Code Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Order Number Package Number Package Description DM74ALS646WM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74ALS646NT N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide |
Số phần tương tự - DM74ALS646 |
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Mô tả tương tự - DM74ALS646 |
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