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MCF5272 Integrated Microprocessor Product Brief

MOTOROLA

MCF5272 Architecture

management logic to reenable the core’s clock; execution resumes with the next instruction. This

allows rapid return from power-down state as compared to a dynamic implementation that must

perform power-on reset processing before software can handle the interrupt request. If interrupts

are enabled at the appropriate priority level, program control passes to the relevant interrupt

service routine.

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Stop mode is entered by the disabling of the external clock input and is achieved by software

setting a bit in a control register. Program execution stops after the current instruction. In stop

mode, neither the core nor peripherals are active. The MCF5272 consumes very little power in this

mode. To resume normal operation, the external interrupts cause the power management logic to

re-enable the external clock input. The MCF5272 resumes program execution from where it

entered stop mode (if no interrupt are pending), or starts interrupt exception processing if

interrupts are pending.

1.2.2.5

Parallel Input/Output Ports

The MCF5272 has up to three 16-bit general-purpose parallel ports, each line of which can be programmed

as either an input or output. Some port lines have dedicated pins and others are shared with other MCF5272

functions. Some outputs have high drive current capability.

1.2.2.6

Interrupt Inputs

The MCF5272 has flexible latched interrupt inputs each of which can generate a separate, maskable

interrupt with programmable interrupt priority level and triggering edge (falling or rising). Each interrupt

has its own interrupt vector.

1.2.3

UART Module

The MCF5272 has two full-duplex UART modules with an on-chip baud rate generator providing both

standard and non-standard baud rates up to 5 Mbps. The module is functionally equivalent to the MC68681

DUART with enhanced features including 24-byte Tx and Rx FIFOs. Data formats can be 5, 6, 7, or 8 bits

with even, odd, or no parity and up to 2 stop bits in 1/16-bit increments. Receive and transmit FIFOs

minimize CPU service calls. A wide variety of error detection and maskable interrupt capability is provided.

Using a programmable prescaler or an external source, the MCF5272 system clock supports various baud

rates. Modem support is provided with request-to-send (RTS) and clear-to-send (CTS) lines available

externally. Full-duplex autoecho loopback, local loopback, and remote loopback modes can be selected.

The UART can be programmed to interrupt or wake-up the CPU on various normal or abnormal events. To

reduce power consumption, the UART can be disabled by software if not in use.

1.2.4

Timer Module

The timer module contains five timers arranged in two submodules. One submodule contains a

programmable software watchdog timer. The other contains four independent, identical general-purpose

timer units, each containing a free-running 16-bit timer for use in various modes, including capturing the

timer value with an external event, counting external events, or triggering an external signal or interrupting

the CPU when the timer reaches a set value. Each unit has an 8-bit prescaler for deriving the clock input

frequency from the system clock or external clock input. The output pin associated with each timer has

programmable modes.

To reduce power consumption, the timer module can be disabled by software.

Freescale Semiconductor, Inc.

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