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AD5235-EP bảng dữ liệu(PDF) 4 Page - Analog Devices

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AD5235-EP bảng dữ liệu(HTML) 4 Page - Analog Devices

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AD5235-EP
Rev. 0 | Page 4 of 16
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
POWER SUPPLIES
Single-Supply Power Range
VDD
VSS = 0 V
3.0
5.5
V
Dual-Supply Power Range
VDD/VSS
±2.25
±2.75
V
Positive Supply Current
IDD
VIH = VDD or VIL = GND
3.5
8
μA
Negative Supply Current
ISS
VIH = VDD or VIL = GND, VDD = +2.5 V,
VSS = −2.5 V
3.5
7
μA
EEMEM Store Mode Current
IDD (store)
VIH = VDD or VIL = GND, VSS = GND,
ISS ≈ 0
35
mA
ISS (store)
VDD = +2.5 V, VSS = −2.5 V
−35
mA
EEMEM Restore Mode Current7
IDD (restore)
VIH = VDD or VIL = GND, VSS = GND,
ISS ≈ 0
0.3
3
9
mA
ISS (restore)
VDD = +2.5 V, VSS = −2.5 V
−0.3
−3
−9
mA
Power Dissipation8
PDISS
VIH = VDD or VIL = GND
18
50
μW
Power Supply Sensitivity5
PSS
ΔVDD = 5 V ± 10%
0.002
0.01
%/%
DYNAMIC CHARACTERISTICS5, 9
Bandwidth
BW
−3 dB, VDD/VSS = ±2.5 V
125
kHz
Total Harmonic Distortion
THDW
VA = 1 V rms, VB = 0 V, f = 1 kHz
0.05
%
VW Settling Time
tS
VA = VDD, VB = 0 V,
VW = 0.50% error band,
Code 0x000 to Code 0x200
4
μs
Resistor Noise Density
eN_WB
TA = 25°C
20
nV/√Hz
Crosstalk (CW1/CW2)
CT
VA = VDD, VB = 0 V, measured VW1
with VW2 making full-scale change
90
nV-s
Analog Crosstalk
CTA
VDD = VA1 = +2.5 V,
VSS = VB1 = −2.5 V, measured
VW1 with VW2 = 5 V p-p @ f = 1 kHz,
Code 1 = 0x200, Code 2 = 0x3FF
−81
dB
1 Typicals represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. IW ~ 50 μA for VDD = 2.7 V and IW ~ 400 μA for VDD = 5 V (see Figure 23).
3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = VSS. DNL specification limits of
±1 LSB maximum are guaranteed monotonic operating conditions (see Figure 24).
4 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-
referenced bipolar signal adjustment.
5 Guaranteed by design and not subject to production test.
6 Common-mode leakage current is a measure of the dc leakage from any Terminal A, Terminal B, or Terminal W to a common-mode bias level of VDD/2.
7 EEMEM restore mode current is not continuous. Current is consumed while EEMEM locations are read and transferred to the RDAC register (see Figure 20). To
minimize power dissipation, a NOP, Instruction 0 (0x0) should be issued immediately after Instruction 1 (0x1).
8 PDISS is calculated from (IDD × VDD) + (ISS × VSS).
9 All dynamic characteristics use VDD = +2.5 V and VSS = −2.5 V.


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