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74LVX573MX bảng dữ liệu(PDF) 2 Page - Fairchild Semiconductor

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Giải thích chi tiết về linh kiện  Low Voltage Octal Latch with 3-STATE Outputs
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Functional Description
The LVX573 contains eight D-type latches. When the
enable (LE) input is HIGH, data on the Dn inputs enters the
latches. In this condition the latches are transparent, i.e., a
latch output will change state each time its D input
changes. When LE is LOW the latches store the informa-
tion that was present on the D inputs a setup time preced-
ing the HIGH-to-LOW transition of LE. The 3-STATE
buffers are controlled by the Output Enable (OE) input.
When OE is LOW, the buffers are enabled. When OE is
HIGH the buffers are in the high impedance mode but this
does not interfere with entering new data into the latches.
Truth Table
H
HIGH Voltage
L
LOW Voltage
Z
High Impedance
X
Immaterial
O0
Previous O0 before HIGH-to-LOW transition of Latch Enable
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs
Outputs
OE
LE
D
On
LH
H
H
LH
L
L
LL
X
O0
HX
X
Z


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