Pin Descriptions

Pin Names

Description

D

Data Inputs

CP

Clock Pulse Input

OE

3-STATE Output Enable Input

O

3-STATE Outputs

Truth Table

Inputs

Outputs

D

n

CP

OE

O

n

H

N

LH

L

N

LL

XX

H

Z

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Z = High Impedance

Functional Description

The LVQ374 consists of eight edge-triggered flip-flops with

individual D-type inputs and 3-STATE true outputs. The buff-

ered clock and buffered Output Enable are common to all

flip-flops. The eight flip-flops will store the state of their indi-

vidual D-type inputs that meet the setup and hold time re-

quirements on the LOW-to-HIGH Clock (CP) transition. With

the Output Enable (OE) LOW, the contents of the eight

flip-flops are available at the outputs. When the OE is HIGH,

the outputs go to the high impedance state. Operation of the

OE input does not affect the state of the flip-flops.

Logic Diagram

DS011360-5

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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