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ISL1902 bảng dữ liệu(PDF) 2 Page - Intersil Corporation |
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ISL1902 bảng dữ liệu(HTML) 2 Page - Intersil Corporation |
2 / 25 page ISL1902 2 FN7981.2 March 20, 2013 Pin Configuration ISL1902 (24 LD QSOP TOP VIEW VDD PRELOAD OFFREF VREF IOUT CS+ CS- REFIN LPOUT OC FB2 FB1 OUT INRUSH GND AC OVP LREF RAMP VERR DELADJ PWMOUT LOUT LFB 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 Pin Descriptions PIN # SYMBOL DESCRIPTION 1 VDD VDD is the power connection for the IC. To optimize noise immunity, bypass VDD to GND with a ceramic capacitor as close to the VDD and GND pins as possible. 2 PRELOAD The output control signal to drive an external FET placed in parallel with the LED load. This feature allows the output capacitor to be quickly discharged to prevent continued low level illumination of the LEDs due to stored energy in the output capacitor. 3 OFFREF Sets the reference level to disable the driver at light loading. The turn-off reference can be set at any level between 0V and 0.6V, corresponding to 0% to 100% of output loading. This feature is normally used in triac-based wall dimmer applications to disable the output before the dimmer becomes unstable due to insufficient holding current. OFFREF triggers PRELOAD to discharge the output capacitance with an external FET. 4 VREF The 5.40V reference voltage output having ±100mV tolerance over line, load and operating temperature. Bypass to GND with a 0.1µF to 3.3µF low ESR capacitor. 5 IOUT The output of the differential current sensing circuit. A pair of resistors and capacitors is placed on this output to form two low pass filters. IOUT creates the current feedback signals for the control loop and is normally filtered and scaled prior to inputing at FB1 and FB2 through separate input resistors to allow for different BWs. 6, 7 CS+, CS- The differential inputs for the current sense circuit. This circuit generates a DC feedback signal for the control loop as well as the input to the CrCM circuit to determine the critical conduction operating point. CS± has a common mode range of -0.3V to 0.5V and a differential input range of 0V to1.5V 8 REFIN The reference voltage input that sets the control loop reference. Normally connected to LPOUT or an external control reference. 9 LPOUT Output of the digital low-pass filter. The output ranges from 0V to 0.5V in proportion to the AC conduction angle. This output may be used as is or manipulated (such as when used with an external light sensor or temperature monitor) and applied to REFIN to be used as the reference for the control loop. 10 OC This is the input to the peak overcurrent comparator. The overcurrent comparator threshold is set at 600mV nominal. Peak OCP is required for cycle-by-cycle protection. It also protects against low AC line conditions. OCP includes leading-edge-blanking (LEB), which blocks the signal at the beginning of the OUT pulse for the duration of the blanking period, and also while the OUT pulse is low. 11, 12 FB2, FB1 FBx is the inverting input to the error amplifier (EAs). The current feedback signal is applied to EA1 and EA2. EA1 is the primary error amplifier and is used for steady state operation. EA2 is the secondary control loop for operation during transients. Normally EA1 is configured for low bandwidth operation, about 20Hz, to obtain power factor correction. EA2 is configured for higher BW to respond to transients. Both error amplifiers are externally compensated to give the user complete flexibility. 13 DELADJ Sets delay before a new switching cycles starts. This adjustment allows the user to delay the next switching cycle until the switching FET drain-source voltage reaches a minimum value to allow quasi-ZVS (Zero Voltage Switching) operation. A resistor to ground programs the delay. Pulling DELADJ to VREF disables the CrCM oscillator. 14 VERR Output of the error amplifiers and the control voltage input to the inverting input of the PWM comparator. VERR requires an external pull-up resistor to VREF. 15 RAMP This is the input for the sawtooth waveform for the PWM comparator. Using an RC from VREF, a sawtooth waveform is created for use by the PWM. It is compared to the error amplifier output, VERR, to create the PWM control signal. The RAMP pin is shorted to GND at the termination of the PWM signal. 16 LFB The inverting input to the uncommitted linear amplifier. |
Số phần tương tự - ISL1902 |
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Mô tả tương tự - ISL1902 |
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