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74FR543SPC bảng dữ liệu(PDF) 2 Page - Fairchild Semiconductor |
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74FR543SPC bảng dữ liệu(HTML) 2 Page - Fairchild Semiconductor |
2 / 6 page www.fairchildsemi.com 2 Pin Descriptions Functional Description The 74FR543 contains two sets of D-type latches, with separate input and output controls for each. For data flow from A-to-B, for example, the A-to-B Enable (CEAB) input must be LOW in order to enter data from the A Port or take data from the B Port as indicated in the Data I/O Control Table. With CEAB LOW, a LOW signal on (LEAB) input makes the A-to-B latches transparent; a subsequent LOW- to-HIGH transition of the LEAB line puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the B out- put buffers are active and reflect the data present on the output of the A latches. Control of data flow from B-to-A is similar, but using the CEBA, LEBA and OEBA. Data I/O Control Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Logic Diagram Pin Names Description OEAB, OEBA Output Enable Inputs LEAB, LEBA Latch Enable Inputs CEAB, CEBA Chip Enable Inputs A0–A7 Side A Inputs or 3-STATE Outputs B0–B7 Side B Inputs or 3-STATE Outputs Inputs Latch Output CEAB LEAB OEAB Status Buffers H X X Latched High Z X H X Latched — L L X Transparent — XX H — High Z L X L — Driving |
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Mô tả tương tự - 74FR543SPC |
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