© 1999 Fairchild Semiconductor Corporation

DS009457

www.fairchildsemi.com

April 1988

Revised July 1999

74F08

Quad 2-Input AND Gate

General Description

This device contains four independent gates, each of which

performs the logic AND function.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol

IEEE/IEC

Connection Diagram

Unit Loading/Fan Out

Order Number

Package Number

Package Description

74F08SC

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

74F08SJ

M14D

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74F08PC

N14A

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Pin Names

Description

U.L.

HIGH/LOW

Inputs

1.0/1.0

20

µA/−0.6 mA

Outputs

50/33.3

−1 mA/20 mA