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74ALVCH16244T bảng dữ liệu(PDF) 1 Page - Fairchild Semiconductor |
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74ALVCH16244T bảng dữ liệu(HTML) 1 Page - Fairchild Semiconductor |
1 / 6 page © 2002 Fairchild Semiconductor Corporation DS500625 www.fairchildsemi.com September 2001 Revised February 2002 74ALVCH16244 Low Voltage 16-Bit Buffer/Line Driver with Bushold General Description The ALVCH16244 contains sixteen non-inverting buffers with 3-STATE outputs to be employed as a memory and address driver, clock driver, or bus oriented transmitter/ receiver. The device is nibble (4-bit) controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. The ALVCH16244 data inputs include active bushold cir- cuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level. The 74ALVCH16244 is designed for low voltage (1.65V to 3.6V) VCC applications with output capability up to 3.6V. The 74ALVCH16244 is fabricated with an advanced CMOS technology to achieve high speed operation while maintain- ing low CMOS power dissipation. Features s 1.65V to 3.6V VCC supply operation s 3.6V tolerant control inputs and outputs s Bushold on data inputs eliminating the need for external pull-up/pull-down resistors s tPD 3 ns max for 3.0V to 3.6V VCC 3.7 ns max for 2.3V to 2.7V VCC 6.0 ns max for 1.65V to 1.95V VCC s Uses patented noise/EMI reduction circuitry s Latch-up conforms to JEDEC JED78 s ESD performance: Human body model > 2000V Machine model > 200V Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Order Number Package Number Package Description 74ALVCH16244T MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Pin Names Description OEn Output Enable Input (Active LOW) I0–I15 Bushold Inputs O0–O15 Outputs |
Số phần tương tự - 74ALVCH16244T |
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Mô tả tương tự - 74ALVCH16244T |
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