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MCP2025 bảng dữ liệu(PDF) 5 Page - Microchip Technology |
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MCP2025 bảng dữ liệu(HTML) 5 Page - Microchip Technology |
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5 / 36 page  2012 Microchip Technology Inc. DS22306A-page 5 MCP2025 1.2 Pin Descriptions Please refer to Table 1-2 for the pinout overview. 1.2.1 VBB Battery Positive Supply Voltage pin. An external diode is connected in series to prevent the device from being reversely powered (refer to Figure 1-9). 1.2.2 VREG Positive Supply Voltage Regulator Output pin. An on- chip Low Dropout Regulator (LDO) gives +5.0 or +3.3V 70 mA regulated voltage on this pin. 1.2.3 VSS Ground pin. 1.2.4 TXD Transmit data input pin (TTL level, HV compliant, adaptive pull-up). The transmitter reads the data stream on the TXD pin and sends it to the LIN bus. The LBUS pin is low (dominant) when TXD is low, and high (recessive) when TXD is high. The Transmit Data Input pin has an internal adaptive pull-up to an internally-generated 4.2V (approximately). When TXD is ‘0’, a weak pull-up (~900 kΩ) is used to reduce current. When TXD is ‘1’ a stronger pull-up (~300 kΩ) is used to maintain the logic level. A series reverse-blocking diode allows applying TXD input voltages greater than the internally generated 4.2V and renders the TXD pin HV compliant up to 30V (see Block Diagram). 1.2.5 RXD Receive Data Output pin. The RXD pin is a standard CMOS output pin and it follows the state of the LBUS pin. 1.2.6 LBUS LIN Bus pin. LBUS is a bidirectional LIN bus Interface pin and is controlled by the signal TXD. It has an open collector output with a current limitation. To reduce ElectroMagnetic Emission, the slopes during signal changes are controlled, and the LBUS pin has corner- rounding control for both falling and rising edges. The internal LIN receiver observes the activities on the LIN bus, and generates the output signal RXD that follows the state of the LBUS. A first degree 160 KHz, low-pass input filter optimizes ElectroMagnetic immunity. 1.2.7 CS/LWAKE Chip Select and Local Wake-up Input pin (TTL level, high voltage tolerant). This pin controls the device state transition. Refer to Figure 1-1. An internal pull-down resistor will keep the CS/LWAKE pin low to ensure that no disruptive data will be present on the bus while the microcontroller is executing a POWER-ON RESET and I/O initialization sequence. When CS/LWAKE is ‘1’, a weak pull-down (~600 KΩ) is used to reduce current. When CS/LWAKE is ‘0’ a stronger pull-down (~300 KΩ) is used to maintain the logic level. This pin may also be used as a local wake-up input (See Figure 1-9). The microcontroller will set the I/O pin to control the CS/LWAKE. An external switch, or other source, can then wake-up both the transceiver and the microcontroller. 1.2.8 RESET RESET OUTPUT pin. This is an open drain output pin. It indicates the internal voltage has reached a valid, stable level. As long as the internal voltage is valid (above 0.8VREG), this pin will present high impedance; otherwise the RESET pin switches to ground. TABLE 1-2: PINOUT OVERVIEW Note: CS/LWAKE should NOT be tied directly to pin VREG as this could force the MCP2025 into OPERATION mode before the microcontroller is initialized. PIN Name PIN Number PIN Type Function VREG 8 Output Voltage regulator output VSS 3 Power Ground VBB 1 Power Battery TXD 6 Input, HV-tolerant Transmit data input RXD 5 Output Receive data output LBUS 4 I/O, HV LIN Bus CS/LWAKE 2 TTL Input, HV-tolerant Chip Select and Local Wake-up input RESET 7 Open Drain Output, HV- tolerant Reset output |
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Mô tả tương tự - MCP2025 |
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