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2

Functional Description

The ACTQ823 consists of nine D-type edge-triggered flip-

flops. These have 3-STATE outputs for bus systems orga-

nized with inputs and outputs on opposite sides. The buff-

ered clock (CP) and buffered Output Enable (OE) are

common to all flip-flops. The flip-flops will store the state of

their individual D inputs that meet the setup and hold time

requirements on the LOW-to-HIGH CP transition. With OE

LOW, the contents of the flip-flops are available at the out-

puts. When OE is HIGH, the outputs go to the high imped-

ance state. Operation of the OE input does not affect the

state of the flip-flops. In addition to the Clock and Output

Enable pins, there are Clear (CLR) and Clock Enable (EN)

pins. These devices are ideal for parity bus interfacing in

high performance systems.

When CLR is LOW and OE is LOW, the outputs are LOW.

When CLR is HIGH, data can be entered into the flip-flops.

When EN is LOW, data on the inputs is transferred to the

outputs on the LOW-to-HIGH clock transition. When the

EN is HIGH, the outputs do not change state, regardless of

the data or clock input transitions.

Function Table

H

= HIGH Voltage Level

Z

= High Impedance

L

= LOW Voltage Level

 = LOW-to-HIGH Transition

X

= Immaterial

NC

= No Change

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Inputs

Internal

Output

Function

OE

CLR

EN

CP

D

Q

O

H

X

L



L

L

Z

High Z

H

X

L



H

H

Z

High Z

H

L

X

X

X

L

Z

Clear

L

L

X

X

X

L

L

Clear

H

H

H

X

X

NC

Z

Hold

L

H

H

X

X

NC

NC

Hold

H

H

L



L

L

Z

Load

H

H

L



H

H

Z

Load

L

H

L



L

L

L

Load

L

H

L



H

H

H

Load