AD5260/AD5262

Rev. A | Page 8 of 24

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AD5262

TOP VIEW

(Not to Scale)

W1

B1

SDI

CLK

SHDN

A1

W2

B2

A2

SDO

CS

PR

GND

Figure 8. AD5262 Pin Configuration

Table 6. AD5262 Pin Function Descriptions

Pin No.

Mnemonic

Description

1

SDO

Serial Data Output. Open-drain transistor requires a pull-up resistor.

2

A1

A Terminal RDAC 1.

3

W1

Wiper RDAC 1, Address A0 = 0.

4

B1

B Terminal RDAC 1.

5

6

SHDN

Active Low Input. Terminal A, open-circuit. Shutdown controls variable Resistor 1 through Resistor R2.

7

CLK

Serial Clock Input, Positive Edge Triggered.

8

SDI

Serial Data Input.

9

CS

Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded, based on the

Address Bit A0, and loaded into the target RDAC register.

10

PR

Active Low Preset to Midscale. Sets RDAC registers to 0x80.

11

GND

Ground.

12

13

Logic Supply Voltage. Needs to be same voltage as the digital logic controlling the AD5262.

14

B2

B Terminal RDAC 2.

15

W2

Wiper RDAC 2, Address A0 = 1.

16

A2

A Terminal RDAC 2.