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AD5262BRU50 bảng dữ liệu(PDF) 4 Page - Analog Devices |
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AD5262BRU50 bảng dữ liệu(HTML) 4 Page - Analog Devices |
4 / 24 page AD5260/AD5262 Rev. A | Page 4 of 24 Parameter Symbol Conditions Min Typ1 Max Unit DYNAMIC CHARACTERISTICS6, 10 Bandwidth –3 dB BW RAB = 20 kΩ/50 kΩ/200 kΩ 310/130/30 kHz Total Harmonic Distortion THDW VA = 1 VRMS, VB = 0 V, f = 1 kHz, RAB = 20 kΩ 0.014 % VW Settling Time tS VA = +5 V, VB = −5 V, ±1 LSB error band, RAB = 20 kΩ 5 μs Crosstalk11 CT VA = VDD, VB = 0 V, measure VW with adjacent RDAC making full-scale code change (AD5262 only) 1 nV-sec Analog Crosstalk CTA VA1 = VDD, VB1 = 0 V, measure VW1 with VW2 = 5 V p-p at f = 10 kHz, RAB = 20 kΩ/200 kΩ (AD5262 only) –64 dB Resistor Noise Voltage eN_WB RWB = 20 kΩ, f = 1 kHz 13 nV/√Hz INTERFACE TIMING CHARACTERISTICS6, 12 Specifications apply to all parts Clock Frequency fCLK 25 MHz Input Clock Pulse Width tCH, tCL Clock level high or low 20 ns Data Setup Time tDS 10 ns Data Hold Time tDH 10 ns CLK to SDO Propagation Delay13 tPD RL = 1 kΩ, CL< 20 pF 1 160 ns CS Setup Time tCSS 5 ns CS High Pulse Width tCSW 20 ns Reset Pulse Width tRS 50 ns CLK Fall to CS Rise Hold Time tCSH 0 ns CS Rise to Clock Rise Setup tCS1 10 ns 1 Typical values represent average readings at 25°C and VDD = +5 V, VSS = −5 V. 2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. IW = VDD/R for both VDD = +5 V and VSS = −5V. 3 VAB = VDD, wiper = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 Measured at the Ax terminals. All Ax terminals are open-circuit in shutdown mode. 8 Worst-case supply current consumed when all logic-input levels set at 2.4 V, which is the standard characteristic of CMOS logic. 9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 10 All dynamic characteristics use VDD = +5 V, VSS = −5 V, VL = +5 V. 11 Measured at VW where an adjacent VW is making a full-scale voltage change. 12 See Figure 5 for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using VL = 5 V. 13 Propagation delay depends on value of VDD, RL, and CL. |
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