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OP177FS bảng dữ liệu(PDF) 2 Page - Analog Devices

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OP177FS bảng dữ liệu(HTML) 2 Page - Analog Devices

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OP177A
OP177B
Parameter
Symbol
Conditions
Min
Typ
Max
Min
Typ
Max
Units
Input Offset Voltage
VOS
410
10
25
µV
Long-Term Input Offset Voltage Stability
∆V
OS/Time
(Note 1)
0.2
0.2
µV/Mo
Input Offset Current
IOS
0.3
1.0
0.3
1.5
nA
Input Bias Current
IB
–0.2
1.5
–0.2
2.0
nA
Input Noise Voltage
en
fo = 1 Hz to 100 Hz
2
118
150
118
150
nV rms
Input Noise Current
in
fo = 1 Hz to 100 Hz
2
38
3
8
pA rms
Input Resistance Differential-Mode
RIN
(Note 3)
26
45
26
45
M
Input Resistance Common-Mode
RINCM
200
200
G
Input Voltage Range
IVR
(Note 4)
±13
±14
±13
±14
V
Common-Mode Rejection Ratio
CMRR
VCM = ± 13 V
130
140
130
140
dB
Power Supply Rejection Ratio
PSRR
VS = ± 3 V to ± 18 V
120
125
115
125
dB
Large Signal Voltage Gain
AVO
RL ≥ 2 kΩ, VO = ± 10 V
5
5000
12000
5000
12000
V/mV
Output Voltage Swing
VO
RL ≥ 10 kΩ± 13.5
±14.0
±13.5 ±14.0
V
RL ≥ 2 kΩ± 12.5
±13.0
±12.5 ±13.0
V
RL ≥ 1 kΩ± 12.0
±12.5
±12.0 ±12.5
V
Slew Rate
SR
RL ≥ 2 kΩ
2
0.1
0.3
0.1
0.3
V/
µs
Closed-Loop Bandwidth
BW
AVCL = +1
2
0.4
0.6
0.4
0.6
MHz
Open-Loop Output Resistance
RO
60
60
Power Consumption
PD
VS = ± 15 V, No Load
50
60
50
60
mW
VS = ± 3 V, No Load
3.5
4.5
3.5
4.5
mW
Supply Current
ISY
VS = ± 15 V, No Load
1.6
2.0
1.6
2.0
mA
Offset Adjustment Range
Rp = 20 k
±3
±3mV
NOTES
1Long-Term Input Offset Voltage Stability refers to the averaged trend line of V
OS vs. Time over extended periods after the first 30 days of operation. Excluding the
initial hour of operation, changes in VOS during the first 30 operating days are typically less than 2.0 µV.
2Sample tested.
3Guaranteed by design.
4Guaranteed by CMRR test condition.
5To insure high open-loop gain throughout the
±10 V output range, A
VO is tested at –10 V ≤ VO ≤ 0 V, 0 V ≤ VO ≤ +10 V, and –10 V ≤ VO ≤ +10 V.
Specifications subject to change without notice.
REV. B
–2–
OP177–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ VS = 15 V, TA = +25 C, unless otherwise noted)
ELECTRICAL CHARACTERISTICS
OP177A
OP177B
Parameter
Symbol
Conditions
Min
Typ
Max
Min
Typ
Max
Units
Input Offset Voltage
VOS
10
20
25
55
µV
Average Input Offset Voltage Drift
TCVOS
(Note 1)
0.03
0.1
0.1
0.3
µV/°C
Input Offset Current
IOS
0.5
1.5
0.5
2.0
nA
Average Input Offset Current Drift
TCIOS
(Note 2)
1.5
25
1.5
25
pA/
°C
Input Bias Current
IB
–0.2
2.4
4
–0.2
2.4
4
nA
Average Input Bias Current Drift
TCIB
(Note 2)
8
25
8
25
pA/
°C
Input Voltage Range
IVR
(Note 3)
±13
±13.5
±13
±13.5
V
Common-Mode Rejection Ratio
CMRR
VCM = ± 13 V
120
140
120
140
dB
Power Supply Rejection Ratio
PSRR
VS = ± 3 V to ± 18 V
120
125
110
120
dB
Large-Signal Voltage Gain
AVO
RL ≥ 2 kΩ, VO = ± 10 V
4
2000
6000
2000
6000
V/mV
Output Voltage Swing
VO
RL ≥ 2 kΩ± 12
±13.0
±12
±13.0
V
Power Consumption
PD
VS = ± 15 V, No Load
60
75
60
75
mW
Supply Current
ISY
VS = ± 15 V, No Load
2.0
2.5
2.0
2.5
mA
NOTES
1TCV
OS is 100% tested.
2Guaranteed by endpoint limits.
3Guaranteed by CMRR test condition.
4To insure high open-loop gain throughout the
± 10 V output range, A
VO is tested at –10 V ≤ VO ≤ 0 V, 0 V ≤ VO ≤ +10 V, and –10 V ≤ VO ≤ +10 V.
Specifications subject to change without notice.
(@ VS =
15 V, –55
°C ≤ T
A
≤ +125 C, unless otherwise noted)


Số phần tương tự - OP177FS

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Mô tả tương tự - OP177FS

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