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OP177AZ bảng dữ liệu(PDF) 4 Page - Analog Devices |
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OP177AZ bảng dữ liệu(HTML) 4 Page - Analog Devices |
4 / 12 page OP177–SPECIFICATIONS REV. B –4– ELECTRICAL CHARACTERISTICS OP177E OP177F OP177G Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Units Input Offset Voltage VOS 10 20 15 40 20 100 µV Average Input Offset Voltage Drift TCVOS (Note 1) 0.03 0.1 0.1 0.3 0.7 1.2 µV/°C Input Offset Current IOS 0.5 1.5 0.5 2.2 0.5 4.5 nA Average Input Offset Current Drift TCIOS (Note 2) 1.5 25 1.5 40 1.5 85 pA/ °C Input Bias Current IB –0.2 2.4 4 –0.2 2.4 4 2.4 ±6.0 nA Average Input Bias Current Drift TCIB (Note 2) 8 25 8 40 15 60 pA/ °C Input Voltage Range IVR (Note 3) ±13 ±13.5 ±13 ±13.5 ±13.0 ±13.5 V Common-Mode Rejection Ratio CMRR VCM = ± 13 V 120 140 120 140 110 140 dB Power Supply Rejection Ratio PSRR VS = ± 3 V to ± 18 V 120 125 110 120 106 115 dB Large-Signal Voltage Gain AVO RL ≥ 2 kΩ, VO = ± 10 V 4 2000 6000 2000 6000 1000 4000 V/mV Output Voltage Swing VO RL ≥ 2 kΩ± 12 ±13.0 ±12 ±13.0 ±12.0 ±13.0 V Power Consumption PD VS = ± 15 V, No Load 60 75 60 75 60 75 mW Supply Current ISY VS = ± 15 V, No Load 2.0 2.5 2.0 2.5 2.0 2.5 mA NOTES 1OP177E: TCV OS is 100% tested. 2Guaranteed by endpoint limits. 3Guaranteed by CMRR test condition. 4To insure high open-loop gain throughout the ± 10 V output range, A VO is tested at –10 V ≤ VO ≤ 0 V, 0 V ≤ VO ≤ +10 V, and –10 V ≤ VO ≤ +10 V. Specifications subject to change without notice. Figure 2. Typical Offset Voltage Test Circuit Figure 3. Optional Offset Nulling Circuit (@ VS = 15 V, –40 °C ≤ T A ≤ +85 C, unless otherwise noted) |
Số phần tương tự - OP177AZ |
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Mô tả tương tự - OP177AZ |
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