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ADS42B49IRGCT bảng dữ liệu(PDF) 8 Page - Texas Instruments |
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ADS42B49IRGCT bảng dữ liệu(HTML) 8 Page - Texas Instruments |
8 / 66 page ADS42B49 SBAS558B – DECEMBER 2012 – REVISED JANUARY 2013 www.ti.com TIMING REQUIREMENTS: LVDS and CMOS Modes Typical values are at +25°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, sampling frequency = 250 MSPS, sine wave input clock, CLOAD = 3.3 pF, and RLOAD = 100 Ω, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, and DRVDD = 1.7 V to 2 V. PARAMETER DESCRIPTION MIN TYP MAX UNIT tA Aperture delay 0.5 0.8 1.1 ns Aperture delay matching Between two channels of the same device ±70 ps Between two devices at the same temperature and Variation of aperture delay ±150 ps DRVDD supply tJ Aperture jitter 120 fS rms Time to valid data after coming out of STANDBY 50 µs mode Wakeup time Time to valid data after coming out of GLOBAL 100 µs power-down mode Clock Default latency after reset 11 cycles ADC latency(1) Clock Digital functions enabled (EN DIGITAL = 1) 19 cycles DDR LVDS MODE(2)(3) Data setup time on rising Data valid to zero-crossing of differential output clock tSU_RISE 0.32 0.68 ns edge of CLKOUTP (CLKOUTP – CLKOUTM)(4) Data hold time on rising Zero-crossing of differential output clock tHO_RISE 0.5 0.82 ns edge of CLKOUTP (CLKOUTP – CLKOUTM) to data becoming invalid(4) Data setup time on falling Data valid to zero-crossing of differential output clock tSU_FALL 0.63 1.04 ns edge of CLKOUTP (CLKOUTP – CLKOUTM)(4) Data hold time on falling Zero-crossing of differential output clock tHO_FALL 0.18 0.58 ns edge of CLKOUTP (CLKOUTP – CLKOUTM) to data becoming invalid(4) Input clock rising edge cross-over to output clock tPDI Clock propagation delay 7.6 8.9 10.2 ns (CLKOUTP – CLKOUTM) rising edge cross-over Duty cycle of differential clock LVDS bit clock duty cycle 57 % (CLKOUTP – CLKOUTM) tFALL, Data fall time, Rise time measured from –100 mV to +100 mV 0.13 ns tRISE Data rise time 1 MSPS ≤ Sampling frequency ≤ 250 MSPS tCLKRISE, Output clock rise time, Rise time measured from –100 mV to +100 mV 0.13 ns tCLKFALL Output clock fall time 1 MSPS ≤ Sampling frequency ≤ 250 MSPS tRISE, Data rise time, Rise time measured from 20% to 80% of DRVDD 0.13 ns tFALL Data fall time 1 MSPS ≤ Sampling frequency ≤ 250 MSPS tCLKRISE, Output clock rise time, Rise time measured from 20% to 80% of DRVDD 0.13 ns tCLKFALL Output clock fall time 1 MSPS ≤ Sampling frequency ≤ 250 MSPS PARALLEL CMOS MODE Input clock rising edge cross-over to output clock tPDI Clock propagation delay 5.9 8.3 10.6 ns rising edge cross-over Duty cycle of output clock, CLKOUT Output clock duty cycle 50 % 1 MSPS ≤ Sampling frequency ≤ 200 MSPS Rise time measured from 20% to 80% of DRVDD tRISE, Data rise time, Fall time measured from 80% to 20% of DRVDD 0.7 ns tFALL Data fall time 1 MSPS ≤ Sampling frequency ≤ 200 MSPS Rise time measured from 20% to 80% of DRVDD tCLKRISE, Output clock rise time Fall time measured from 80% to 20% of DRVDD 0.7 ns tCLKFALL Output clock fall time 1 MSPS ≤ Sampling frequency ≤ 200 MSPS (1) Overall latency = ADC latency + tPDI. At 250 MSPS, tPDI is greater than two clock periods. Therefore, overall latency at 250 MSPS = ADC latency + 2 clock cycles. (2) Measurements are done with a transmission line of a 100- Ω characteristic impedance between the device and load. Setup and hold time specifications take into account the effect of jitter on the output data and clock. (3) Setup and hold values in DDR LVDS mode are taken with a delayed output clock by writing register 42h, value 30h. (4) Data valid refers to a logic high of +100 mV and a logic low of –100 mV. 8 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42B49 |
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