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ADS4229 bảng dữ liệu(PDF) 6 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  Dual-Channel, 14-Bit, 250-MSPS Ultralow-Power ADC with Analog Input Buffer
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ADS4229 bảng dữ liệu(HTML) 6 Page - Texas Instruments

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ADS42B49
SBAS558B – DECEMBER 2012 – REVISED JANUARY 2013
www.ti.com
ELECTRICAL CHARACTERISTICS: ADS42B49 (250 MSPS) (continued)
Typical values are at +25°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, –1-dBFS differential
analog input, LVDS interface, and 0-dB gain, unless otherwise noted. Minimum and maximum values are across the full
temperature range:
TMIN = –40°C to TMAX = +85°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, and DRVDD = 1.8 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
10-MHz full-scale signal on channel under observation;
Crosstalk
> 85
dB
170-MHz full-scale signal on other channel
Recovery to within 1%
Input overload recovery
1
Clock cycle
(of full-scale) for 6-dB overload with sine-wave input
AC power-supply rejection
PSRR
For 50-mVPP signal on AVDD supply
30
dB
ratio
ENOB
Effective number of bits
fIN = 170 MHz
11.4
LSBs
ELECTRICAL CHARACTERISTICS: GENERAL
Typical values are at +25°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, and –1-dBFS
differential analog input, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN =
–40°C to TMAX = +85°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, and DRVDD = 1.8 V.
PARAMETER
MIN
TYP
MAX
UNIT
ANALOG INPUTS
VID
Differential input voltage range
2
VPP
Differential input resistance (at 170 MHz)
1.2
k
Ω
Differential input capacitance (at 170 MHz)
2.2
pF
Analog input bandwidth
700
MHz
(with 50-
Ω source impedance, and 50-Ω termination)
VCM
Common-mode output voltage
1.9(1)
V
VCM output current capability
10
mA
DC ACCURACY
Offset error
–20
3
20
mV
EGREF
Gain error as a result of internal reference inaccuracy alone
–2
2
%FS
EGCHAN
Gain error of channel alone
–5
%FS
Temperature coefficient of EGCHAN
0.005
Δ%/°C
POWER SUPPLY
IAVDD
Analog supply current
186
225
mA
IAVDD_BUF
Analog buffer supply current
67
90
mA
LVDS interface, 350-mV swing with 100-
Ω external termination,
151
180
mA
fIN = 2.5 MHz
IDRVDD
Output buffer supply current
CMOS interface, 8-pF external load capacitance,
128
mA
fIN = 2.5 MHz
(2)
Analog power
353
mW
Analog buffer power
224
mW
Digital power, LVDS interface, 350-mV swing with 100-
Ω external termination, fIN = 2.5 MHz
272
mW
Digital power, CMOS interface, 8-pF external load capacitance,(2) fIN = 2.5 MHz
230
mW
Total power, LVDS interface, 350-mV swing with 100-
Ω external termination, fIN = 2.5 MHz
850
925
mW
Global power-down
20
mW
(1)
After the HIGH PERF MODE[10:0] bits are set.
(2)
In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency, and the
supply voltage (see the CMOS Interface Power Dissipation section in the Application Information).
6
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Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: ADS42B49


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