công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

ADS4226 bảng dữ liệu(PDF) 8 Page - Texas Instruments

Click here to check the latest version.
tên linh kiện ADS4226
Giải thích chi tiết về linh kiện  Dual-Channel, 14-Bit, 250-MSPS Ultralow-Power ADC with Analog Input Buffer
Download  66 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  TI [Texas Instruments]
Trang chủ  http://www.ti.com
Logo TI - Texas Instruments

ADS4226 bảng dữ liệu(HTML) 8 Page - Texas Instruments

Back Button ADS4226 Datasheet HTML 4Page - Texas Instruments ADS4226 Datasheet HTML 5Page - Texas Instruments ADS4226 Datasheet HTML 6Page - Texas Instruments ADS4226 Datasheet HTML 7Page - Texas Instruments ADS4226 Datasheet HTML 8Page - Texas Instruments ADS4226 Datasheet HTML 9Page - Texas Instruments ADS4226 Datasheet HTML 10Page - Texas Instruments ADS4226 Datasheet HTML 11Page - Texas Instruments ADS4226 Datasheet HTML 12Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 8 / 66 page
background image
ADS42B49
SBAS558B – DECEMBER 2012 – REVISED JANUARY 2013
www.ti.com
TIMING REQUIREMENTS: LVDS and CMOS Modes
Typical values are at +25°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, sampling frequency = 250 MSPS, sine
wave input clock, CLOAD = 3.3 pF, and RLOAD = 100 Ω, unless otherwise noted. Minimum and maximum values are across the
full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, and DRVDD = 1.7 V to 2 V.
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
tA
Aperture delay
0.5
0.8
1.1
ns
Aperture delay matching
Between two channels of the same device
±70
ps
Between two devices at the same temperature and
Variation of aperture delay
±150
ps
DRVDD supply
tJ
Aperture jitter
120
fS rms
Time to valid data after coming out of STANDBY
50
µs
mode
Wakeup time
Time to valid data after coming out of GLOBAL
100
µs
power-down mode
Clock
Default latency after reset
11
cycles
ADC latency(1)
Clock
Digital functions enabled (EN DIGITAL = 1)
19
cycles
DDR LVDS MODE(2)(3)
Data setup time on rising
Data valid to zero-crossing of differential output clock
tSU_RISE
0.32
0.68
ns
edge of CLKOUTP
(CLKOUTP – CLKOUTM)(4)
Data hold time on rising
Zero-crossing of differential output clock
tHO_RISE
0.5
0.82
ns
edge of CLKOUTP
(CLKOUTP – CLKOUTM) to data becoming invalid(4)
Data setup time on falling
Data valid to zero-crossing of differential output clock
tSU_FALL
0.63
1.04
ns
edge of CLKOUTP
(CLKOUTP – CLKOUTM)(4)
Data hold time on falling
Zero-crossing of differential output clock
tHO_FALL
0.18
0.58
ns
edge of CLKOUTP
(CLKOUTP – CLKOUTM) to data becoming invalid(4)
Input clock rising edge cross-over to output clock
tPDI
Clock propagation delay
7.6
8.9
10.2
ns
(CLKOUTP – CLKOUTM) rising edge cross-over
Duty cycle of differential clock
LVDS bit clock duty cycle
57
%
(CLKOUTP – CLKOUTM)
tFALL,
Data fall time,
Rise time measured from –100 mV to +100 mV
0.13
ns
tRISE
Data rise time
1 MSPS ≤ Sampling frequency ≤ 250 MSPS
tCLKRISE,
Output clock rise time,
Rise time measured from –100 mV to +100 mV
0.13
ns
tCLKFALL
Output clock fall time
1 MSPS ≤ Sampling frequency ≤ 250 MSPS
tRISE,
Data rise time,
Rise time measured from 20% to 80% of DRVDD
0.13
ns
tFALL
Data fall time
1 MSPS
≤ Sampling frequency ≤ 250 MSPS
tCLKRISE,
Output clock rise time,
Rise time measured from 20% to 80% of DRVDD
0.13
ns
tCLKFALL
Output clock fall time
1 MSPS
≤ Sampling frequency ≤ 250 MSPS
PARALLEL CMOS MODE
Input clock rising edge cross-over to output clock
tPDI
Clock propagation delay
5.9
8.3
10.6
ns
rising edge cross-over
Duty cycle of output clock, CLKOUT
Output clock duty cycle
50
%
1 MSPS ≤ Sampling frequency ≤ 200 MSPS
Rise time measured from 20% to 80% of DRVDD
tRISE,
Data rise time,
Fall time measured from 80% to 20% of DRVDD
0.7
ns
tFALL
Data fall time
1 MSPS ≤ Sampling frequency ≤ 200 MSPS
Rise time measured from 20% to 80% of DRVDD
tCLKRISE,
Output clock rise time
Fall time measured from 80% to 20% of DRVDD
0.7
ns
tCLKFALL
Output clock fall time
1 MSPS ≤ Sampling frequency ≤ 200 MSPS
(1)
Overall latency = ADC latency + tPDI. At 250 MSPS, tPDI is greater than two clock periods. Therefore, overall latency at 250 MSPS =
ADC latency + 2 clock cycles.
(2)
Measurements are done with a transmission line of a 100-
Ω characteristic impedance between the device and load. Setup and hold time
specifications take into account the effect of jitter on the output data and clock.
(3)
Setup and hold values in DDR LVDS mode are taken with a delayed output clock by writing register 42h, value 30h.
(4)
Data valid refers to a logic high of +100 mV and a logic low of –100 mV.
8
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: ADS42B49


Số phần tương tự - ADS4226

nhà sản xuấttên linh kiệnbảng dữ liệuGiải thích chi tiết về linh kiện
logo
Texas Instruments
ADS4226 TI1-ADS4226 Datasheet
3Mb / 97P
[Old version datasheet]   Dual-Channel, 12-/14-Bit, 65/125/160MSPS Ultralow-Power ADC
MARCH2011
ADS4226 TI1-ADS4226 Datasheet
3Mb / 104P
[Old version datasheet]   Dual-Channel, 14-/12-Bit, 160/125/65MSPS Ultralow-Power ADC
ADS4226 TI1-ADS4226 Datasheet
1Mb / 67P
[Old version datasheet]   Dual-Channel, 12-Bit, 250-MSPS Ultralow-Power ADC
ADS4226 TI1-ADS4226 Datasheet
4Mb / 105P
[Old version datasheet]   Dual-Channel, 14-/12-Bit, 160/125/65MSPS Ultralow-Power ADC
ADS4226IRGC25 TI1-ADS4226IRGC25 Datasheet
3Mb / 97P
[Old version datasheet]   Dual-Channel, 12-/14-Bit, 65/125/160MSPS Ultralow-Power ADC
MARCH2011
More results

Mô tả tương tự - ADS4226

nhà sản xuấttên linh kiệnbảng dữ liệuGiải thích chi tiết về linh kiện
logo
Texas Instruments
ADS4249 TI1-ADS4249 Datasheet
1Mb / 67P
[Old version datasheet]   Dual-Channel, 14-Bit, 250-MSPS Ultralow-Power ADC
ADS4249 TI1-ADS4249_16 Datasheet
1Mb / 74P
[Old version datasheet]   Dual-Channel, 14-Bit, 250-MSPS Ultralow-Power ADC
ADS4229 TI1-ADS4229_14 Datasheet
1Mb / 67P
[Old version datasheet]   Dual-Channel, 12-Bit, 250-MSPS Ultralow-Power ADC
ADS4229 TI1-ADS4229 Datasheet
1Mb / 67P
[Old version datasheet]   Dual-Channel, 12-Bit, 250-MSPS Ultralow-Power ADC
OCTOBER2011
ADS4229 TI1-ADS4229_15 Datasheet
1Mb / 67P
[Old version datasheet]   Dual-Channel, 12-Bit, 250-MSPS Ultralow-Power ADC
ADS4229IRGC25 TI1-ADS4229IRGC25 Datasheet
1Mb / 67P
[Old version datasheet]   Dual-Channel, 12-Bit, 250-MSPS Ultralow-Power ADC
ADS42B49 TI1-ADS42B49 Datasheet
1Mb / 65P
[Old version datasheet]   250-MSPS Ultralow-Power ADC
ADS61B29 TI-ADS61B29 Datasheet
1Mb / 61P
[Old version datasheet]   14-/12-Bit, 250-MSPS ADCs With Integrated Analog Buffer
ADS61B49 TI-ADS61B49_09 Datasheet
1Mb / 62P
[Old version datasheet]   14-/12-Bit, 250-MSPS ADCs With Integrated Analog Buffer
ADS4222 TI1-ADS4222_15 Datasheet
3Mb / 88P
[Old version datasheet]   Dual-Channel, 14-/12-Bit, 160/125/65 MSPS Ultralow-Power ADC
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66


bảng dữ liệu tải về

Go To PDF Page


Link URL




Chính sách bảo mật
ALLDATASHEET.VN
Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com