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ADP3303AARU-REEL bảng dữ liệu(PDF) 6 Page - Analog Devices |
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ADP3303AARU-REEL bảng dữ liệu(HTML) 6 Page - Analog Devices |
6 / 8 page ADP3303A –6– REV. A THEORY OF OPERATION The new anyCAP LDO ADP3303A uses a single control loop for regulation and reference functions. The output voltage is sensed by a resistive voltage divider consisting of R1 and R2, which is varied to provide the available output voltage options. Feedback is taken from this network by way of a series diode (D1) and a second resistor divider (R3 and R4) to the input of an amplifier. gm PTAT VOS R4 R3 D1 R1 ATTENUATION (VBANDGAP/VOUT) R2 (a) COMPENSATION CAPACITOR NONINVERTING WIDEBAND DRIVER Q1 INPUT CLOAD OUTPUT ADP3303A RLOAD PTAT CURRENT GND Figure 20. Functional Block Diagram A very high gain error amplifier is used to control this loop. The amplifier is constructed in such a way that at equilibrium it produces a large, temperature proportional input “offset voltage” that is repeatable and very well controlled. The temperature- proportional offset voltage is combined with the complementary diode voltage to form a “virtual bandgap” voltage, implicit in the network, although it never appears explicitly in the circuit. Ultimately, this patented design makes it possible to control the loop with only one amplifier. This technique also improves the noise characteristics of the amplifier by providing more flexibil- ity on the trade-off of noise sources that leads to a low noise design. The R1, R2 divider is chosen in the same ratio as the bandgap voltage to the output voltage. Although the R1, R2 resistor divider is loaded by the diode D1, and a second divider consist- ing of R3 and R4, the values are chosen to produce a tempera- ture stable output. This unique arrangement specifically corrects for the loading of the divider so that the error resulting from base current loading in conventional circuits is avoided. The patented amplifier controls a new and unique noninverting driver that drives the pass transistor, Q1. The use of this special noninverting driver enables the frequency compensation to include the load capacitor in a pole splitting arrangement to achieve reduced sensitivity to the value, type and ESR of the load capacitance. Most LDOs place strict requirements on the range of ESR val- ues for the output capacitor because they are difficult to sta- bilize due to the uncertainty of load capacitance and resistance. Moreover, the ESR value, required to keep conventional LDOs stable, changes depending on load and temperature. These ESR limitations make designing with LDOs more difficult because of their unclear specifications and extreme variations over temperature. This is no longer true with the ADP3303A anyCAP LDO. It can be used with virtually any capacitor, with no constraint on the minimum ESR. The innovative design allows the circuit to be stable with just a small 1 µF capacitor on the output. Addi- tional advantages of the pole splitting scheme include superior line noise rejection and very high regulator gain, which leads to excel- lent line and load regulation. An impressive ±1.4% accuracy is guaranteed over line, load and temperature. Additional features of the circuit include current limit, thermal shutdown and noise reduction. Compared to standard solutions that give warning after the output has lost regulation, the ADP3303A provides improved system performance by enabling the ERR Pin to give warning before the device loses regulation. As the chip’s temperature rises above 165 °C, the circuit acti- vates a soft thermal shutdown, indicated by a signal low on the ERR Pin, to reduce the current to a safe level. APPLICATION INFORMATION The ADP3303A is very easy to use. The only external compo- nent required for stability is a small 1 µF bypass capacitor on the output. If the shutdown feature is not used, the shutdown pin (Pin 8) should be tied to the input pin. CAPACITOR SELECTION Bypass Capacitor (C1): connecting a 0.47 µF capacitor from the IN pins (Pins 10 and 11) to ground greatly improves its line transient response and reduces the circuit’s sensitivity to PC board layout. A larger capacitor could be used if line transients of longer duration are expected. Output Capacitor (C2): as will all members of the anyCAP low dropout regulator family, the ADP3303A is stable with any type of output capacitor down to zero ESR. A small 1 µF output capacitor is required for stability. Larger capacitors with low ESR are recommended for improved load transient response. For space limited applications, Multilayer Ceramic Capacitors (MLCC) are a good choice. For low temperature operations OS-CON capacitors offer better performance. Noise Reduction Capacitor (CNR): to reduce the ADP3303A’s low output noise by 6 dB–10 dB, a noise gain limiting capacitor can be connected between the feedback (FB) pin (Pin 6) and the OUT pins as shown in Figure 21. Low leakage capacitors in the 100 pF–500 pF range provide the best performance. Larger capacitors will slow down the output transient response. CNR is not needed in low noise applications where fast load transients are not expected. ADP3303A 8 7 6 9 ERR OUT IN 4 5 11 10 FB R1 CNR VOUT = +5V SD GND C1 VIN R2 R3 330k 1 F Figure 21. Noise Reduction Circuit OUTPUT VOLTAGE SELECTION The ADP3303A is characterized by having the output voltage divider placed externally. The output voltage will be divided by R1 and R2 and fed back to the FB pin. In order to have the lowest possible sensitivity of output voltage versus any temperature variation, it is important that the parallel resistance of R1 and R2 is always 44 k Ω. |
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