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ADMC401BST bảng dữ liệu(PDF) 5 Page - Analog Devices |
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ADMC401BST bảng dữ liệu(HTML) 5 Page - Analog Devices |
5 / 60 page ADMC401 –5– REV. B Parameter Min Max Unit Clock Signals t CK is defined as 0.5tCKI. The ADMC401 uses an input clock with a frequency equal to half the instruction rate; a 13 MHz clock (which is equivalent to 76.9 ns) yields a 38.5 ns processor cycle (equivalent to 26 MHz). t CK values within the range of 0.5t CKI period should be substituted for all relevant timing parameters to obtain specification value. Example: t CKH = 0.5tCK – 10 ns = 0.5 (38.5 ns) – 10 ns = 9.25 ns. Timing Requirements: t CKI CLKIN Period 76.9 150 ns t CKIL CLKIN Width Low 20 ns t CKIH CLKIN Width High 20 ns Switching Characteristics: t CKL CLKOUT Width Low 0.5t CK – 10 ns t CKH CLKOUT Width High 0.5t CK – 10 ns t CKOH CLKIN High to CLKOUT High 0 20 ns Control Signals Timing Requirement: t RSP RESET Width Low 5t CK 1 ns PWM Shutdown Signals Timing Requirements: tPWMTPW PWMTRIP Width Low tCK ns tPIOPWM PIO Width Low 2tCK ns ADC Signals Timing Requirements: tCSI Internal Convert Start Width High 2tCK ns tCSE External Convert Start Width High 2tCK ns NOTE 1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal oscillator start-up time). CLKIN CLKOUT tCKOH tCKI tCKIH tCKIL tCKH tCKL Figure 1. Clock Signals |
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Mô tả tương tự - ADMC401BST |
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