ADMC200

REV. B

–6–

registers respectively. The twos complement data is left justified

and the LSB is set to zero. The relationship between input volt-

age and output coding is shown in Figure 5.

0 11111111110

000000000000

100000000000

OUTPUT

CODE

FULL-SCALE

TRANSITION

0V

2.5

5V–1LSB

INPUT VOLTAGE

FS = 5V

LSB =

5V

2048

Figure 5. Transfer Function

Sample and Hold

After powering up the ADMC200, bring the

RESET pin low for

a minimum of two clock cycles in order to enable A/D conver-

sions. Before initiating the first conversion (CONVST) after a

reset, the SHA time of 20 system clock cycles must occur. A

conversion is initiated by bringing CONVST high for a mini-

mum of one system clock cycle. The SHA goes into hold mode

at the falling edge of clock.

Following completion of the A/D conversion process, a mini-

mum of 20 system clock cycles are required before initiating an-

other conversion in order to allow the sample and hold circuitry

to reacquire the input signals.

If a CONVST is initiated before the 20 clock cycles have

elapsed, the embedded control sequencer will delay conversion

until this requirement is met.

PWM TIMER BLOCK OVERVIEW

The PWM timers have 12-bit resolution and support program-

mable pulse deletion and deadtime. The ADMC200 generates

three center-based signals A, B, and C based upon user-supplied

duty cycles values. The three signals are then complemented

and adjusted for programmable deadtime to produce the six

outputs. The ADMC200 PWM master switching frequency can

range from 2.5 kHz to 20 kHz, when using a 10 MHz system

clock. The master frequency selection is set as a fraction of the

PWMTM register. If the system clock is 10 MHz, then the

minimum edge resolution available is 100 ns.

The output format of the PWM block is active LO. There is an

external input to the PWM timers (STOP) that will disable all

six outputs within one system clock when the input is HIGH.

The ADMC200 has a PWM Synchronization output

(PWMSYNC) which brings out the master switching frequency

from the PWM timers. The width of the PWMSYNC pulse is

equal to one system clock cycle. For example, if the system clock

is 10 MHz, the PWMSYNC width would be equal to 100 ns.

PWM Master Switching Period Selection

The switching time is set by the PWMTM register which should

be loaded with a value equal to the system clock frequency

divided by the desired master switching frequency. For ex-

ample, if the desired switching frequency is 8 kHz and the sys-

tem clock frequency is 10 MHz, then the PWMTM register

should be loaded with 1250 (10 MHz/8 kHz). The PWMCHA,

PWMCHB, and PWMCHC registers are loaded with the

ANALOG INPUT BLOCK

The ADMC200 contains an 11-bit resolution, successive approxi-

mation analog-to-digital (A/D) converter with twos complement

output data format. The analog input range is

±2.5 V (0 V–5 V)

with a 2.5 V offset as defined by REFIN. The on-chip 2.5 V

±

5% reference is utilized by connecting the REFOUT pin to the

REFIN pin.

The A/D conversion time is determined by the system clock fre-

quency, which can range from 6.25 MHz to 12.5 MHz. The

Sample and Hold (SHA) acquisition time is 20 system clock

cycles and is independent of the number of channels sampled

and/or digitized. The input stage to the A/D converter is a four

channel SHA which allows the four channels to be held simulta-

neously and then sequentially digitized. Forty system clock

cycles are required to complete each A/D conversion. The ana-

log channel sampling is flexible and is programmable through

the SYSCTRL register. The minimum number of channels per

conversion is two. The throughput time of the analog acquisi-

tion block can be calculated as follows:

t

where

n = # channels,

× system clock period),

× system clock period) per channel.

A/D Conversions are initiated via the CONVST pin. A syn-

chronizing pulse (PWMSYNC) is provided at the beginning of

each PWM cycle. This pulse can be used to synchronize the

A/D conversion process to the PWM switching frequency.

Operating the A/D Converter

The A/D converter can be set up to convert a sequence of chan-

nels as defined in the SYSCTRL register (see Table V). Always

write 0 to both Bits 0 and 1 of the SYSCTRL register. The de-

fault channel select mode after

RESET is to convert channels V

and W only. This is two-/three-phase mode. Three-/three-phase

mode converts channels U, V, W and/or AUX. Three-/three-

phase mode is achieved by writing a 1 to Bit 3 of the SYSCTRL

register. After the conversion process is complete, the channels

can be read in any order.

There are two methods that can be used to indicate when the

A/D conversions are completed and the data is ready: interrupt

driven and software timing.

Interrupt Driven Method

Interrupts can be used to indicate the end of conversion for a

group of channels. Before beginning any A/D conversions, Bit 7

of the SYSCTRL register must be set to 1 to enable A/D con-

version interrupts. Then, when an A/D conversion is complete,

an interrupt will be generated. After an interrupt is detected

Bit 0 of the SYSSTAT register must be checked to determine if

the A/D converter was the source. Reading the SYSSTAT reg-

ister automatically clears the interrupt flag bits.

Software Timing Method

An alternative method is to use the DSP or microcontroller to

keep track of the amount of time elapsed between CONVST

and the expected completion time (n

Reading Results

The 11-bit A/D conversion results for channels U, V, W and

AUX are stored in the ADCU, ADCV, ADCW and ADCAUX