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ADM1029ARQ bảng dữ liệu(PDF) 8 Page - Analog Devices |
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ADM1029ARQ bảng dữ liệu(HTML) 8 Page - Analog Devices |
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8 / 48 page  REV. 0 ADM1029 –8– R/ W 0 SCL SDA 10 1 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY ADM1029 START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 ADDRESS POINTER REGISTER BYTE 19 1 ACK. BY ADM1029 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY ADM1029 STOP BY MASTER FRAME 3 DATA BYTE 1 9 SCL (CONTINUED) SDA (CONTINUED) Figure 4a. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register R/ W 0 SCL SDA 10 1 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY ADM1029 STOP BY MASTER START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 ADDRESS POINTER REGISTER BYTE 19 1 ACK. BY ADM1029 9 Figure 4b. Writing to the Address Pointer Register Only R/ W 0 SCL SDA 10 1 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 NO ACK. BY MASTER STOP BY MASTER START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 DATA BYTE FROM ADM1029 19 1 ACK. BY ADM1029 9 Figure 4c. Reading Data from a Previously Selected Register The serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a START condition, defined as a high-to-low transition on the serial data line SDA, while the serial clock line SCL remains high. This indicates that an address/data stream will follow. All slave peripherals connected to the serial bus respond to the START condition, and shift in the next eight bits, consisting of a 7-bit address (MSB first) plus an R/ W bit, which deter- mines the direction of the data transfer, i.e., whether data will be written to or read from the slave device. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the Acknowl- edge Bit. All other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. If the R/ W bit is a 0, the master will write to the slave device. If the R/ W bit is a 1 the master will read from the slave device. 2. Data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an acknowledge bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low-to-high transition when the clock is high may be interpreted as a STOP signal. The number of data bytes that can be transmitted over the serial bus in a single READ or WRITE operation is limited only by what the master and slave devices can handle. 3. When all data bytes have been read or written, stop condi- tions are established. In WRITE mode, the master will pull the data line high during the tenth clock pulse to assert a STOP condition. In READ mode, the master device will override the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse. This is known as No Acknowledge. The master will then take the data line low during the low period before the tenth clock pulse, high during the tenth clock pulse to assert a STOP condition. Any number of bytes of data may be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation, because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. |
Số phần tương tự - ADM1029ARQ |
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Mô tả tương tự - ADM1029ARQ |
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