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AD9888KS-140 bảng dữ liệu(PDF) 10 Page - Analog Devices |
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10 / 32 page REV. A AD9888 –10– The offset controls provide a ±63 LSB adjustment range. This range is connected with the full-scale range, so if the input range is doubled (from 0.5 V to 1.0 V), the offset step size is also doubled (from 2 mV per step to 4 mV per step). Figure 2 illustrates the interaction of gain and offset controls. The magnitude of an LSB in offset adjustment is proportional to the full-scale range, so changing the full-scale range also changes the offset. The change is minimal if the offset setting is near midscale. When changing the offset, the full-scale range is not affected, but the full-scale level is shifted by the same amount as the zero-scale level. GAIN 1.0 0.0 00h FFh 0.5 OFFSET = 00h OFFSET = 3Fh OFFSET = 7Fh OFFSET = 00h OFFSET = 7Fh OFFSET = 3Fh Figure 2. Gain and Offset Control Sync-on-Green The Sync-on-Green input operates in two steps. First, it sets a baseline clamp level off of the incoming video signal with a negative peak detector. Second, it sets the sync trigger level (nominally 150 mV above the negative peak). The exact trigger level is variable and can be programmed via register 11H. The Sync-on-Green input must be ac-coupled to the green analog input through its own capacitor as shown in Figure 3. The value of the capacitor must be 1 nF ± 20%. If Sync-on-Green is not used, this connection is not required and the SOGIN pin should be left unconnected. (Note: the Sync-on-Green signal is always negative polarity.) For more details, see the Sync Processing section. RAIN BAIN GAIN SOG 47nF 47nF 47nF 1nF Figure 3. Typical Clamp Configuration for RGB/YUV Applications Clock Generation A Phase Locked Loop (PLL) is employed to generate the pixel clock. The Hsync input provides a reference frequency to the PLL. A Voltage Controlled Oscillator (VCO) generates a much higher pixel clock frequency. This pixel clock is divided by the PLL divide value (registers 01H and 02H) and phase compared with the Hsync input. Any error is used to shift the VCO frequency and maintain lock between the two signals. The stability of this clock is a very important element in provid- ing the clearest and most stable image. During each pixel time, there is a period during which the signal is slewing from the old pixel amplitude and settling at its new value. Then there is a time when the input voltage is stable, before the signal must slew to a new value (Figure 4). The ratio of the slewing time to the stable time is a function of the bandwidth of the graphics DAC and the bandwidth of the transmission system (cable and termination). It is also a function of the overall pixel rate. Clearly, if the dynamic characteristics of the system remain fixed, then the slewing and settling time is likewise fixed. This time must be subtracted from the total pixel period, leaving the stable period. At higher pixel frequencies, the total cycle time is shorter, and the stable pixel time becomes shorter as well. PIXEL CLOCK INVALID SAMPLE TIMES Figure 4. Pixel Sampling Times Any jitter in the clock reduces the precision with which the sampling time can be determined, and must also be subtracted from the stable pixel time. Considerable care has been taken in the design of the AD9888’s clock generation circuit to minimize jitter. As indicated in Fig- ure 5, the clock jitter of the AD9888 is less than 9% of the total pixel time in all operating modes, making the reduction in the valid sampling time due to jitter negligible. PIXEL CLOCK – MHz 0 2 4 6 8 10 12 14 Figure 5. Pixel Clock Jitter vs. Frequency The PLL characteristics are determined by the loop filter design, by the PLL Charge Pump Current and by the VCO range setting. The loop filter design is illustrated in Figure 6. Recommended settings of VCO range and charge pump current for VESA standard display modes are listed in Table IV. |
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