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AD9020JE bảng dữ liệu(PDF) 3 Page - Analog Devices |
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AD9020JE bảng dữ liệu(HTML) 3 Page - Analog Devices |
3 / 12 page Test AD9020JE/JZ AD9020KE/KZ Parameter (Conditions) Temp Level Min Typ Max Min Typ Max Units DYNAMIC PERFORMANCE (continued) Harmonic Distortion fIN = 2.3 MHz +25 °C I 61 67 61 67 dBc fIN = 10.3 MHz +25 °C I 55 59 55 59 dBc fIN = 15.3 MHz +25 °C I 49 53 49 53 dBc Two-Tone Intermodulation Distortion Rejection 7 +25 °C V 70 70 dBc Differential Phase +25 °C V 0.5 0.5 Degree Differential Gain +25 °CV 1 1 % ENCODE INPUT Logic “1” Voltage Full VI 2.0 2.0 V Logic “0” Voltage Full VI 0.8 0.8 V Logic “1” Current Full VI 20 20 µA Logic “0” Current Full VI 800 800 µA Input Capacitance +25 °CV 5 5 pF Pulse Width (High) +25 °C I 66ns Pulse Width (Low) +25 °C I 66ns DIGITAL OUTPUTS Logic “1” Voltage (IOH = 2 mA) Full VI 2.4 2.4 V Logic “0” Voltage (IOL = 6 mA) Full VI 0.4 V POWER SUPPLY +VS Supply Current +25 °C I 440 530 440 530 mA Full VI 542 542 mA –VS Supply Current +25 °C I 140 170 140 170 mA Full VI 177 177 mA Power Dissipation +25 °C I 2.8 3.3 2.8 3.3 W Full VI 3.4 3.4 W Power Supply Rejection Ratio (PSRR) 8 Full VI 6 10 6 10 mV/V NOTES 1Absolute maximum ratings are limiting values to be applied individually, and beyond which the service ability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2Typical thermal impedances (part soldered onto board): 68-pin leaded ceramic chip carrier: θ JC = 1°C/W; θJA = 17°C/W (no air flow); θJA = 15°C/W (air flow = 500 LFM). 68-pin ceramic LCC: θ JC = 2.6°C/W; θJA = 15°C/W (no air flow); θJA = 13°C/W (air flow = 500 LFM). 33/4 REF, 1/2REF, and 1/4REF reference ladder taps are driven from dc sources at +0.875 V, 0 V, and –0.875 V, respectively. Accuracy of the overflow comparator is not tested and not included in linearity specifications. 4Measured with ANALOG IN = +V SENSE. 5Output delay measured as worst-case time from 50% point of the rising edge of ENCODE to 50% point of the slowest rising or falling edge of D 0–D9. Output skew measured as worst-case difference in output delay among D 0–D9. 6RMS signal to rms noise with analog input signal 1 dB below full scale at specified frequency. 7Intermodulation measured with analog input frequencies of 2.3 MHz and 3.0 MHz at 7 dB below full scale. 8Measured as the ratio of the worst-case change in transition voltage of a single comparator for a 5% change in +V S or –VS. Specifications subject to change without notice. REV. A –3– AD9020 |
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