AD800/AD802

REV. B

–3–

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –6 V

Maximum Junction Temperature

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150

°C

Ceramic DIP Package . . . . . . . . . . . . . . . . . . . . . . +175

°C

Storage Temperature Range . . . . . . . . . . . . –65

°C to +150°C

Lead Temperature Range (Soldering 60 sec) . . . . . . . +300

°C

ESD Rating

AD800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 V

AD802 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 V

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only; functional operation

of the device at these or any other conditions above those indicated in the

operational section of this specification is not implied. Exposure to an absolute

maximum rating condition for an extended period may adversely affect device

reliability.

RECOVERED CLOCK

SKEW,

t

RCS

DATAOUT 50%

(PIN 2)

CLKOUT 50%

(PIN 5)

SETUP TIME

t

SU

Figure 1. Recovered Clock Skew and Setup

(See Previous Page)

PIN DESCRIPTIONS

Number

Mnemonic

Description

1

DATAOUT

Differential Retimed Data Output

2

DATAOUT

Differential Retimed Data Output

Digital Ground

4

CLKOUT

Differential Recovered Clock Output

5

CLKOUT

Differential Recovered Clock Output

Digital Ground

10

ASUBST

Analog Substrate

11

Loop Damping Capacitor Input

12

Loop Damping Capacitor Input

13

Analog Ground

14

Digital Ground

15

16

DATAIN

Differential Data Input

17

DATAIN

Differential Data Input

18

SUBST

Digital Substrate

19

FRAC

Differential Frequency Acquisition

Indicator Output

20

FRAC

Differential Frequency Acquisition

Indicator Output

THERMAL CHARACTERISTICS

θ

JC

θ

JA

SOIC Package

22

°C/W

75

°C/W

Cerdip Package

25

°C/W

90

°C/W

Use of a heatsink may be required depending on operating

environment.

GLOSSARY

Maximum and Minimum Specifications

Maximum and minimum specifications result from statistical

analyses of measurements on multiple devices and multiple test

systems. Typical specifications indicate mean measurements.

Maximum and minimum specifications are calculated by adding

or subtracting an appropriate guardband from the typical

specification. Device-to-device performance variation and test

system-to-test system variation contribute to each guardband.

Nominal Center Frequency

This is the frequency that the VCO will operate at with no input

Tracking Range

This is the range of input data rates over which the PLL will

remain in lock.

Capture Range

This is the range of input data rates over which the PLL can

acquire lock.

Static Phase Error

This is the steady-state phase difference, in degrees, between the

recovered clock sampling edge and the optimum sampling

instant, which is assumed to be halfway between the rising and

falling edges of a data bit. Gate delays between the signals that

define static phase error, and IC input and output signals

prohibit direct measurement of static phase error.

Data Transition Density,

This is a measure of the number of data transitions, from “0” to

“1” and from “1” to “0,” over many clock periods.

ρ is the ratio

(0

≤ ρ ≤ 1) of data transitions to clock periods.

Jitter

This is the dynamic displacement of digital signal edges from

their long term average positions, measured in degrees rms, or

Unit Intervals (UI). Jitter on the input data can cause dynamic

phase errors on the recovered clock sampling edge. Jitter on the

recovered clock causes jitter on the retimed data.

Output Jitter

This is the jitter on the retimed data, in degrees rms, due to a

specific pattern or some psuedo-random input data sequence

(PRN Sequence).

Jitter Tolerance

Jitter tolerance is a measure of the PLL’s ability to track a jittery

input data signal. Jitter on the input data is best thought of as

phase modulation, and is usually specified in unit intervals.

ORDERING GUIDE

Fractional Loop

Device

Center Frequency

Bandwidth

Description

Operating Temperature

Package Option

AD800-45BQ

44.736 MHz

0.1%

20-Pin Cerdip

–40

°C to +85°C

Q-20

AD800-52BR

51.84 MHz

0.1%

20-Pin Plastic SOIC

–40

°C to +85°C

R-20

AD802-155BR

155.52 MHz

0.08%

20-Pin Plastic SOIC

–40

°C to +85°C

R-20

AD802-155KR

155.52 MHz

0.08%

20-Pin Plastic SOIC

0

°C to +70°C

R-20