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AD7887 bảng dữ liệu(PDF) 10 Page - Analog Devices |
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AD7887 bảng dữ liệu(HTML) 10 Page - Analog Devices |
10 / 16 page REV. B AD7887 –10– as the source impedance increases and performance will degrade. Figure 10 shows a graph of the total harmonic distortion versus analog input signal frequency for different source impedances. INPUT FREQUENCY – kHz –90 0.15 42.14 10.89 31.59 21.14 –85 –80 –75 –70 –65 49.86 THD vs. FREQUENCY FOR DIFFERENT SOURCE IMPEDANCES VDD = 5V 5V EXT REFERENCE RIN = 1k , CIN = 100pF RIN = 50 , CIN = 2.2nF RIN = 10 , CIN = 10nF Figure 10. THD vs. Analog Input Frequency On-Chip Reference The AD7887 has an on-chip 2.5 V reference. This reference can be enabled or disabled by clearing or setting the REF bit in the control register respectively. If the on-chip reference is to be used externally in a system then it must be buffered before it is applied elsewhere. If an external reference is applied to the device, then the internal reference is automatically overdriven. However, it is advised to disable the internal reference by setting the REF bit in the control register when an external reference is applied in order to obtain optimum performance from the de- vice. When the internal reference is disabled, SW1 in Figure 11 will open and the input impedance seen at the AIN1/VREF pin is the input impedance of the reference buffer, which is in the region of gigaohms. When the internal reference is enabled the input impedance seen at the pin is typically 10 k Ω. When the AD7887 is operated in two-channel mode, the reference is taken from VDD internally and not from the on-chip 2.5 V reference. 2.5V 10k SW1 AIN1/VREF Figure 11. On-Chip Reference Circuitry POWER-DOWN OPTIONS The AD7887 provides flexible power management to allow the user to achieve the best power performance for a given through- put rate. The power management options are selected by programming the power management bits (i.e., PM1 and PM0) in the control register. Table II summarizes the available options. When the power management bits are programmed for either of the auto power-down modes, the part will enter power-down mode on the 16th rising SCLK edge after the falling edge of CS. The first falling SCLK edge after the CS falling edge will cause the part to power up again. When the AD7887 is in Mode 1, i.e., PM1 = PM0 = 0, the part will enter shutdown on the rising edge of CS and power up from shutdown on the falling edge of CS. If CS is brought high during the conversion in this mode, the part will immediately enter shutdown. Power-Up Times The AD7887 has an approximate 1 µs power-up time when powering up from standby or when using an external reference. When VDD is first connected the AD7887 will power up in Mode 1, i.e., PM1 = PM0 = 0. The part is put into shutdown on the rising edge of CS in this mode. A subsequent power-up from shutdown will take approximately 5 µs. The AD7887 wake-up time is very short in the autostandby mode so it is possible to wake-up the part and carry out a valid conversion in the same read/write operation. POWER VS. THROUGHPUT RATE By operating the AD7887 in autoshutdown, autostandby mode or Mode 1, the average power consumption of the AD7887 decreases at lower throughput rates. Figure 12 shows how, as the throughput rate is reduced, the device remains in its power- down state longer and the average power consumption over time drops accordingly. For example if the AD7887 is operated in a continuous sam- pling mode with a throughput rate of 10 kSPS and a SCLK of 2 MHz (VDD = 5 V), and if PM1 = 1 and PM0 = 0, i.e., the device is in autoshutdown mode, and the on-chip reference is used, the power consumption is calculated as follows. The power dissipation during normal operation is 3.5 mW (VDD = 5 V). If the power-up time is 5 µs, and the remaining conversion plus acquisition time is 15.5 tSCLK, i.e., approximately 7.75 µs, (see Figure 15a), the AD7887 can be said to dissipate 3.5 mW for 12.75 µs during each conversion cycle. If the throughput rate is 10 kSPS, the cycle time is 100 µs and the average power dissi- pated during each cycle is (12.75/100) × (3.5 mW) = 446.25 µW. If VDD = 3 V, SCLK = 2 MHz and the device is again in auto- shutdown mode using the on-chip reference, then the power dissipation during normal operation is 2.1 mW. The AD7887 can now be said to dissipate 2.1 mW for 12.75 µs during each conversion cycle. With a throughput rate of 10 kSPS, the aver- age power dissipated during each cycle is (12.75/100) × (2.1 mW) = 267.75 µW. Figure 12 shows the Power vs. Throughput Rate for automatic shutdown with both 5 V and 3 V supplies. THROUGHPUT – kSPS 10 0 1 10 0.1 0.01 VDD = 5V SCLK = 2MHz VDD = 3V SCLK = 2MHz 20 30 40 50 Figure 12. Power vs. Throughput |
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