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AD7887 bảng dữ liệu(PDF) 5 Page - Analog Devices |
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AD7887 bảng dữ liệu(HTML) 5 Page - Analog Devices |
5 / 16 page REV. B AD7887 –5– PIN FUNCTION DESCRIPTIONS Pin Pin No. Mnemonic Function 1 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7887 and also frames the serial data transfer. When the AD7887 operates in its default mode, the CS pin also acts as the shutdown pin such that with the CS pin high, the AD7887 is in its power-down mode. 2VDD Power Supply Input. The VDD range for the AD7887 is from +2.7 V to +5.25 V. When the AD7887 is con- figured for two-channel operation, this pin also provides the reference source for the part. 3 GND Ground Pin. This pin is the ground reference point for all circuitry on the AD7887. In systems with separate AGND and DGND planes, these planes should be tied together as close as possible to this GND pin. Where this is not possible, this GND pin should connect to the AGND plane. 4 AIN1/VREF Analog Input 1/Voltage Reference Input. In single-channel mode, this pin becomes the reference input/ output. In this case, the user can either access the internal +2.5 V reference or overdrive the internal refer- ence with the voltage applied to this pin. The reference voltage range for an externally-applied reference is +1.2 V to VDD. In two-channel mode, this pin provides the second analog input channel AIN1. The input voltage range on AIN1 is 0 to VDD. 5 AIN0 Analog Input 0. In single-channel mode, this is the analog input and the input voltage range is 0 to VREF. In dual-channel mode, it has an analog input range of 0 to VDD. 6 DIN Data In. Logic Input. Data to be written to the AD7887’s Control Register is provided on this input and is clocked into the register on the rising edge of SCLK (see Control Register section). The AD7887 can be operated as a single-channel read-only ADC by tying the DIN line permanently to GND. 7 DOUT Data Out. Logic Output. The conversion result from the AD7887 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists of four leading zeros followed by the 12 bits of conversion data, which is provided MSB first. 8 SCLK Serial Clock. Logic Input. SCLK provides the serial clock for accessing data from the part and writing serial data to the Control Register. This clock input is also used as the clock source for the AD7887’s conversion process. PIN CONFIGURATION TOP VIEW (Not to Scale) 8 7 6 5 1 2 3 4 CS SCLK AD7887 VDD GND AIN1/VREF DOUT DIN AIN0 |
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