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AD7706BR bảng dữ liệu(PDF) 3 Page - Analog Devices |
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AD7706BR bảng dữ liệu(HTML) 3 Page - Analog Devices |
3 / 32 page –3– REV. A AD7705/AD7706 Parameter B Version1 Units Conditions/Comments LOGIC OUTPUTS (Including MCLK OUT) VOL, Output Low Voltage 0.4 V max ISINK = 800 µA Except for MCLK OUT. 12 V DD = 5 V. VOL, Output Low Voltage 0.4 V max ISINK = 100 µA Except for MCLK OUT. 12 V DD = 3 V. VOH, Output High Voltage 4 V min ISOURCE = 200 µA Except for MCLK OUT. 12 V DD = 5 V. VOH, Output High Voltage VDD–0.6 V min ISOURCE = 100 µA Except for MCLK OUT. 12 V DD = 3 V. Floating State Leakage Current ±10 µA max Floating State Output Capacitance 13 9 pF typ Data Output Coding Binary Unipolar Mode Offset Binary Bipolar Mode SYSTEM CALIBRATION Positive Full-Scale Calibration Limit 14 (1.05 × V REF)/GAIN V max GAIN Is the Selected PGA Gain (1 to 128) Negative Full-Scale Calibration Limit 14 –(1.05 × V REF)/GAIN V max GAIN Is the Selected PGA Gain (1 to 128) Offset Calibration Limit 14 –(1.05 × V REF)/GAIN V max GAIN Is the Selected PGA Gain (1 to 128) Input Span 15 (0.8 × V REF)/GAIN V min GAIN Is the Selected PGA Gain (1 to 128) (2.1 × V REF)/GAIN V max GAIN Is the Selected PGA Gain (1 to 128) POWER REQUIREMENTS VDD Voltage +2.7 to +3.3 V min to V max For Specified Performance Power Supply Currents16 Digital I/Ps = 0 V or VDD. External MCLK IN and CLK DIS = 1 0.32 mA max BUF Bit = 0. fCLKIN = 1 MHz. Gains of 1 to 128 0.6 mA max BUF Bit = 1. fCLKIN = 1 MHz. Gains of 1 to 128 0.4 mA max BUF Bit = 0. fCLKIN = 2.4576 MHz. Gains of 1 to 4 0.6 mA max BUF Bit = 0. fCLKIN = 2.4576 MHz. Gains of 8 to 128 0.7 mA max BUF Bit = 1. fCLKIN = 2.4576 MHz. Gains of 1 to 4 1.1 mA max BUF Bit = 1. fCLKIN = 2.4576 MHz. Gains of 8 to 128 VDD Voltage +4.75 to +5.25 V min to V max For Specified Performance Power Supply Currents16 Digital I/Ps = 0 V or VDD. External MCLK IN and CLK DIS = 1. 0.45 mA max BUF Bit = 0. fCLKIN = 1 MHz. Gains of 1 to 128 0.7 mA max BUF Bit = 1. fCLKIN = 1 MHz. Gains of 1 to 128 0.6 mA max BUF Bit = 0. fCLKIN = 2.4576 MHz. Gains of 1 to 4 0.85 mA max BUF Bit = 0. fCLKIN = 2.4576 MHz. Gains of 8 to 128 0.9 mA max BUF Bit = 1. fCLKIN = 2.4576 MHz. Gains of 1 to 4 1.3 mA max BUF Bit = 1. fCLKIN = 2.4576 MHz. Gains of 8 to 128 Standby (Power-Down) Current 17 16 µA max External MCLK IN = 0 V or VDD. VDD = 5 V. See Figure 9 8 µA max External MCLK IN = 0 V or VDD. VDD = 3 V Power Supply Rejection 18 See Note 19 dB typ NOTES 1Temperature range as follows: B Version, –40 °C to +85°C. 2These numbers are established from characterization or design at initial product release. 3A calibration is effectively a conversion so these errors will be of the order of the conversion noise shown in Tables I and III. This applies after calibration at the temperature of interest. 4Recalibration at any temperature will remove these drift errors. 5Positive Full-Scale Error includes Zero-Scale Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges. 6Full-Scale Drift includes Zero-Scale Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges. 7Gain Error does not include Zero-Scale Errors. It is calculated as Full-Scale Error–Unipolar Offset Error for unipolar ranges and Full-Scale Error–Bipolar Zero Error for bipolar ranges. 8Gain Error Drift does not include Unipolar Offset Drift/Bipolar Zero Drift. It is effectively the drift of the part if zero scale calibrations only were performed. 9This common-mode voltage range is allowed provided that the input voltage on analog inputs does not go more positive than V DD + 30 mV or go more negative than GND – 30 mV. Parts are functional with voltages down to GND – 200 mV, but with increased leakage at high temperature. 10The analog input voltage range on AIN(+) is given here with respect to the voltage on AIN(–) on the AD7705 and is given with respect to the COMMON input on the AD7706. The absolute voltage on the analog inputs should not go more positive than VDD + 30 mV, or go more negative than GND – 30 mV for specified performance, input voltages of GND – 200 mV can be accommodated, but with increased leakage at high temperature. 11V REF = REF IN(+) – REF IN(–). 12These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load. 13Sample tested at +25 °C to ensure compliance. 14After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, the device will output all 0s. 15These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed V DD + 30 mV or go more negative than GND – 30 mV. The offset calibration limit applies to both the unipolar zero point and the bipolar zero point. 16When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the V DD current and power dissipation will vary depending on the crystal or resonator type (see Clocking and Oscillator Circuit section). 17If the external master clock continues to run in standby mode, the standby current increases to 150 µA typical at 5 V and 75 µA at 3 V. When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation depends on the crystal or resonator type (see Standby Mode section). 18Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 25 Hz or 50 Hz. PSRR at 60 Hz will exceed 120 dB with filter notches of 20 Hz or 60 Hz. 19PSRR depends on both gain and V DD. Gain 1 2 4 8–128 VDD = 3 V 86 78 85 93 VDD = 5 V 90 78 84 91 Specifications subject to change without notice. |
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