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AD7703CR bảng dữ liệu(PDF) 9 Page - Analog Devices |
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9 / 16 page AD7703 REV. D –9– Table II. Resonator Loading Capacitors Resonators C1 C2 Ceramic 200 kHz 330 pF 470 pF 455 kHz 100 pF 100 pF 1.0 MHz 50 pF 50 pF 2.0 MHz 20 pF 20 pF Crystals 2.000 MHz 30 pF 30 pF 3.579 MHz 20 pF 20 pF 4.096 MHz None None The input sampling frequency, output data rate, filter character- istics and calibration time are all directly related to the master clock frequency fCLKIN by the ratios given in the specification table under Dynamic Performance. Therefore, the first step in system design with the AD7703 is to select a master clock fre- quency suitable for the bandwidth and output data rate required by the application. ANALOG INPUT RANGES The AD7703 performs conversion relative to an externally sup- plied reference voltage, which allows easy interfacing to ratio- metric systems. In addition, either unipolar or bipolar input voltage ranges may be selected using the BP/UP input. With BP/UP tied low, the input range is unipolar and the span is (VREF–VAGND), where VAGND is the voltage at the device AGND pin. With BP/UP tied high, the input range is bipolar and the span is 2 VREF. In the bipolar mode both positive and negative full scale are directly determined by VREF. This offers superior tracking of positive and negative full scale and better midscale (bipolar zero) stability than bipolar schemes that simply scale and offset the input range. The digital output coding for the unipolar range is unipolar binary and for the bipolar range it is offset binary. Bit weights for the unipolar and bipolar modes are shown in Table I. ACCURACY Sigma-delta ADCs, like VFCs and other integrating ADCs, do not contain any source of nonmonotonicity and inherently offer no missing codes performance. The AD7703 achieves excellent linearity by the use of high quality, on-chip silicon dioxide capacitors, which have a very SYSTEM REF HI AIN SYSTEM REF LO ANALOG MUX A0 A1 SIGNAL CONDITIONING AD7703 SCLK SDATA CAL SC1 SC2 MICRO COMPUTER AIN Figure 12. Typical Connections for System Calibration low capacitance/voltage coefficient. The device also achieves low input drift through the use of chopper-stabilized techniques in its input stage. To ensure excellent performance over time and temperature, the AD7703 uses digital calibration techniques which minimize offset and gain error to typically ±4 LSBs. AUTOCALIBRATION The AD7703 offers both self-calibration and system-calibration facilities. For calibration to occur, the on-chip microcontroller must record the modulator output for two different input condi- tions. These are the “zero scale” and “full scale” points. In uni- polar self-calibration mode, the zero scale point is VAGND and the full-scale point is VREF. With these readings the microcon- troller can calculate the gain slope for the input to output trans- fer function of the converter. In unipolar mode the slope factor is determined by dividing the span between zero and full scale by 2 20. In bipolar mode it is determined by dividing the span by 2 19 since the inputs applied represent only half the total codes. In both unipolar and bipolar modes the slope factor is saved and used to calculate the binary output code when an analog input is applied to the device. Table IV gives the output code size after calibration. System calibration allows the AD7703 to compensate for system gain and offset errors. A typical circuit where this might be used is shown in Figure 12. System calibration performs the same slope factor calculations as self-calibration but uses voltage values presented by the system to the AIN pin for the zero and full-scale points. There are two system calibration modes. The first mode offers system level calibration for system offset and system gain. This is a two step operation. The zero-scale point must be presented to the converter first. It must be applied to the converter before the calibration step is initiated and remain stable until the step is complete. The DRDY output from the device will signal when the step is complete by going low. After the zero-scale point is calibrated the full-scale point is applied and the second calibration step is initiated. Again the voltage must remain stable throughout the calibration step. The two step calibration mode offers another feature. After the sequence has been completed, additional offset calibrations can be performed by themselves to adjust the zero reference point to a new system zero reference value. This second system calibration mode uses an input voltage for the zero-scale calibration point but uses the VREF value for the full-scale point. |
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