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AD7701ARS bảng dữ liệu(PDF) 8 Page - Analog Devices |
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8 / 16 page AD7701 REV. D –8– FILTER CHARACTERISTICS The cutoff frequency of the digital filter is fCLK /409600. At the maximum clock frequency of 4.096 MHz, the cutoff frequency of the filter is 10 Hz and the output rate is 4 kHz. Figure 10 shows the filter frequency response. This is a 6-pole Gaussian response that provides 55 dB of 60 Hz rejection for a 10 Hz cutoff frequency. If the clock frequency is halved to give a 5 Hz cutoff, 60 Hz rejection is better than 90 dB. A normalized s-domain pole-zero plot of the filter is shown in Figure 11. The response of the filter is defined by: H(x) = [1+ 0.693x 2 + 0.240x4 + 0.0555x6 + 0.00962x8 + 0.00133x 10 + 0.000154x12] –0.5 where: x = f/f3 dB, f3 dB = fCLKIN/409600, and f is the frequency of interest. fCLK = 2MHz fCLK = 1MHz fCLK = 4MHz 1 10 100 FREQUENCY – Hz 20 0 –20 –40 –60 –80 –100 –120 –140 –160 Figure 10. Frequency Response of AD7701 Filter jw s 0 j1 j2 –2 –1 –j1 –j2 S1,2 = –1.4663 + j1.8191 S3,4 = –1.7553 + j1.0005 S5,6 = –1.8739 + j0.32272 Figure 11. Normalized Pole-Zero Plot of AD7701 Filter Since the AD7701 contains this on-chip, low-pass filtering, there is a settling time associated with step function inputs, and data will be invalid after a step change until the settling time has elapsed. The AD7701 is therefore unsuitable for high speed multiplexing, where channels are switched and converted se- quentially at high rates, as switching between channels can cause a step change in the input. Rather, it is intended for dis- tributed converter systems using one ADC per channel. However, slow multiplexing of the AD7701 is possible, provided that the settling time is allowed to elapse before data for the new channel is accessed. Sigma-delta ADCs are generally described by the order of the analog low-pass filter. A simple example of a first order sigma- delta ADC is shown in Figure 9. This contains only a first-order low-pass filter or integrator. It also illustrates the derivation of the alternative name for these devices: Charge-Balancing ADCs. C R R AIN INTEGRATOR TO DIGITAL FILTER CLOCK 1-BIT DAC STROBED COMPARATOR +VREF –VREF Figure 9. SEC Basic Charge-Balancing ADC The term charge-balancing comes from the fact that this system is a negative feedback loop that tries to keep the net charge on the integrator capacitor at zero, by balancing charge injected by the input voltage with charge injected by the 1-bit DAC. When the analog input is zero, the only contribution to the integrator output comes from the 1-bit DAC. For the net charge on the integrator capacitor to be zero, the DAC output must spend half its time at +1 V and half its time at –1 V. Assuming ideal components, the duty cycle of the comparator will be 50%. When a positive analog input is applied, the output of the 1-bit DAC must spend a larger proportion of the time at +1 V, so the duty cycle of the comparator increases. When a negative input voltage is applied, the duty cycle decreases. The AD7701 uses a second-order sigma-delta modulator and a sophisticated digital filter that provides a rolling average of the sampled output. After power-up or if there is a step change in the input voltage, there is a settling time that must elapse before valid data is obtained. DIGITAL FILTERING The AD7701’s digital filter behaves like a similar analog filter, with a few minor differences. First, since digital filtering occurs after the A to D conversion process, it can remove noise injected during the conversion process. Analog filtering cannot do this. On the other hand, analog filtering can remove noise super- imposed on the analog signal before it reaches the ADC. Digital filtering cannot do this and noise peaks riding on signals near full scale have the potential to saturate the analog modulator and digital filter, even though the average value of the signal is within limits. To alleviate this problem, the AD7701 has over- range headroom built into the sigma-delta modulator and digital filter which allows overrange excursions of 100 mV. If noise signals are larger than this, consideration should be given to analog input filtering, or to reducing the gain in the input channel so that a full-scale input (2.5 V) gives only a half-scale input to the AD7701 (1.25 V). This will provide an overrange capability greater than 100% at the expense of reducing the dynamic range by 1 bit (50%). |
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