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AD7010 bảng dữ liệu(PDF) 3 Page - Analog Devices |
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AD7010 bảng dữ liệu(HTML) 3 Page - Analog Devices |
3 / 8 page AD7010 REV. B –3– 20k Ω 20k Ω 20pF 20pF AD7010 ITx/QTx 40k Ω ITx / QTx Figure 1. Analog Output Load Test Circuit Q I MODULAR OUTPUT DURING FTEST Figure 2. Modulator State During FTEST MASTER CLOCK TIMING Parameter Limit at TA = –40 C to +85 C Units Description t1 300 ns min MCLK Cycle Time t2 100 ns min MCLK High Time t3 100 ns min MCLK Low Time ABSOLUTE MAXIMUM RATINGS* (TA = +25°C unless otherwise noted) VDD Tx, VDD Rx to AGND . . . . . . . . . . . . . . . –0.3 V to +7 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V Digital I/O Voltage to DGND . . . . . –0.3 V to VDD to + 0.3 V Analog I/O Voltage to AGND . . . . . . . –0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . . –40 °C to +85°C Storage Temperature Range . . . . . . . . . . . . –65 °C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150 °C SSOP θ JA Thermal Impedance . . . . . . . . . . . . . . . . +122°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215 °C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220 °C *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table I. MODE 1 MODE 2 Operation 0 0 Digital JDC Mode 0 1 FTEST 1 X Factory Test, Reserved WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7010 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. (VAA = VDD = +5 V 10%; AGND = DGND = O V. All specifications are TMIN to TMAX unless otherwise noted.) Figure 3. Master Clock (MCLK) Timing Figure 4. Load Circuit for Digital Outputs MCLK t 2 t 1 t 3 TO OUTPUT PIN +2.1V I OH C L 100pF 1.6mA 200 µA I OL |
Số phần tương tự - AD7010 |
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Mô tả tương tự - AD7010 |
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